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authorAndrew Trick <atrick@apple.com>2012-03-07 05:21:36 +0000
committerAndrew Trick <atrick@apple.com>2012-03-07 05:21:36 +0000
commit4c727204271067f3dbf50bd23098b2df8e1cc47a (patch)
tree38df07d4b2485a2cae5ecc559b219f1b692f88b6 /lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
parentdbdca36af8ee6028dbea93c639408ba95e5fda2e (diff)
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misched preparation: modularize schedule verification.
ScheduleDAG will not refer to the scheduled instruction sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152204 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp15
1 files changed, 15 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index c5c5bcd5da..1e5146ed31 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -621,6 +621,21 @@ void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
}
}
+#ifndef NDEBUG
+/// VerifyScheduledSequence - Verify that all SUnits were scheduled and that
+/// their state is consistent with the nodes listed in Sequence.
+///
+void ScheduleDAGSDNodes::VerifyScheduledSequence(bool isBottomUp) {
+ unsigned ScheduledNodes = ScheduleDAG::VerifyScheduledDAG(isBottomUp);
+ unsigned Noops = 0;
+ for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
+ if (!Sequence[i])
+ ++Noops;
+ assert(Sequence.size() - Noops == ScheduledNodes &&
+ "The number of nodes scheduled doesn't match the expected number!");
+}
+#endif // NDEBUG
+
namespace {
struct OrderSorter {
bool operator()(const std::pair<unsigned, MachineInstr*> &A,