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authorStuart Hastings <stuart@apple.com>2011-06-01 18:32:25 +0000
committerStuart Hastings <stuart@apple.com>2011-06-01 18:32:25 +0000
commit090bf19de6e7c75fbf34e753f5e0ad58cc2ca15c (patch)
treed8cb76ab6acd20bda8b7ee01fc0ddbc65928c53f /lib/CodeGen/SelectionDAG/TargetLowering.cpp
parenta3d91cd6a6384478d88ed3022ea4bda8646fedea (diff)
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Fix double FGETSIGN to work on x86_32; followup to 132396.
rdar://problem/5660695 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132411 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/TargetLowering.cpp9
1 files changed, 6 insertions, 3 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 6739f1a8be..bb4df27034 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1759,11 +1759,14 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
Op.getOperand(0).getValueType().isFloatingPoint() &&
!Op.getOperand(0).getValueType().isVector()) {
- if (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) {
+ if (isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32)) {
+ EVT Ty = (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) ?
+ Op.getValueType() : MVT::i32;
// Make a FGETSIGN + SHL to move the sign bit into the appropriate
// place. We expect the SHL to be eliminated by other optimizations.
- SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Op.getValueType(),
- Op.getOperand(0));
+ SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
+ if (Ty != Op.getValueType())
+ Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
unsigned ShVal = Op.getValueType().getSizeInBits()-1;
SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,