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authorSylvestre Ledru <sylvestre@debian.org>2012-09-27 10:14:43 +0000
committerSylvestre Ledru <sylvestre@debian.org>2012-09-27 10:14:43 +0000
commit94c22716d60ff5edf6a98a3c67e0faa001be1142 (patch)
tree2442b2b9658c29e72b1dd7abae926751854c68dc /lib/CodeGen/SelectionDAG/TargetLowering.cpp
parent7e2c793a2b5c746344652b6579e958ee42fafdcc (diff)
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Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/TargetLowering.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 5ed1c03eb1..be3ecf34f7 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1330,7 +1330,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// If all of the unknown bits are known to be zero on one side or the other
// (but not both) turn this into an *inclusive* or.
- // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) if C1&C2 == 0
+ // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Op.getOperand(0),
@@ -1344,7 +1344,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// If all of the demanded bits on one side are known, and all of the set
// bits on that side are also known to be set on the other side, turn this
// into an AND, as we know the bits will be cleared.
- // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 if (C1&C2) == C2
+ // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
// NB: it is okay if more bits are known than are requested
if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
if (KnownOne == KnownOne2) { // set bits are the same on both sides
@@ -1970,7 +1970,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
}
- // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 if ctpop is illegal.
+ // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
}
// (zext x) == C --> x == (trunc C)
@@ -2503,7 +2503,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
N0.getValueType()), Cond);
}
- // Turn (X^C1) == C2 into X == C1^C2 if X&~C1 = 0.
+ // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
if (N0.getOpcode() == ISD::XOR)
// If we know that all of the inverted bits are zero, don't bother
// performing the inversion.