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| author | Chad Rosier <mcrosier@apple.com> | 2013-06-22 18:37:38 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2013-06-22 18:37:38 +0000 |
| commit | 5b3fca50a08865f0db55fc92ad1c037a04e12177 (patch) | |
| tree | 998e3b634ae4bbd2829c36ff98b0fa70e3cda198 /lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | 5729b8ea01739cf9b1171f0a4349275bc8124756 (diff) | |
| download | llvm-5b3fca50a08865f0db55fc92ad1c037a04e12177.tar.gz llvm-5b3fca50a08865f0db55fc92ad1c037a04e12177.tar.bz2 llvm-5b3fca50a08865f0db55fc92ad1c037a04e12177.tar.xz | |
The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index f02e3d6d2e..69ddea4d8e 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1992,7 +1992,7 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: getRegForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const { + MVT VT) const { if (Constraint[0] != '{') return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); |