Split EVT into MVT and EVT, the former representing _just_ a primitive type, while

the latter is capable of representing either a primitive or an extended type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8

18 files changed, 843 insertions, 842 deletions

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d4d13884cb..2d7147d249 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -331,7 +331,7 @@ CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
                                unsigned Depth = 0) {
   // No compile time optimizations on this type.
-  if (Op.getValueType() == EVT::ppcf128)
+  if (Op.getValueType() == MVT::ppcf128)
     return 0;
 
   // fneg is removable even if it has multiple uses.
@@ -833,12 +833,12 @@ SDValue DAGCombiner::combine(SDNode *N) {
 /// otherwise return a null sd operand.
 static SDValue getInputChainForNode(SDNode *N) {
   if (unsigned NumOps = N->getNumOperands()) {
-    if (N->getOperand(0).getValueType() == EVT::Other)
+    if (N->getOperand(0).getValueType() == MVT::Other)
       return N->getOperand(0);
-    else if (N->getOperand(NumOps-1).getValueType() == EVT::Other)
+    else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
       return N->getOperand(NumOps-1);
     for (unsigned i = 1; i < NumOps-1; ++i)
-      if (N->getOperand(i).getValueType() == EVT::Other)
+      if (N->getOperand(i).getValueType() == MVT::Other)
         return N->getOperand(i);
   }
   return SDValue();
@@ -911,7 +911,7 @@ SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
     } else {
       // New and improved token factor.
       Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
-                           EVT::Other, &Ops[0], Ops.size());
+                           MVT::Other, &Ops[0], Ops.size());
     }
 
     // Don't add users to work list.
@@ -1093,7 +1093,7 @@ SDValue DAGCombiner::visitADDC(SDNode *N) {
   if (N->hasNUsesOfValue(0, 1))
     return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
                      DAG.getNode(ISD::CARRY_FALSE,
-                                 N->getDebugLoc(), EVT::Flag));
+                                 N->getDebugLoc(), MVT::Flag));
 
   // canonicalize constant to RHS.
   if (N0C && !N1C)
@@ -1102,7 +1102,7 @@ SDValue DAGCombiner::visitADDC(SDNode *N) {
   // fold (addc x, 0) -> x + no carry out
   if (N1C && N1C->isNullValue())
     return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
-                                        N->getDebugLoc(), EVT::Flag));
+                                        N->getDebugLoc(), MVT::Flag));
 
   // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
   APInt LHSZero, LHSOne;
@@ -1119,7 +1119,7 @@ SDValue DAGCombiner::visitADDC(SDNode *N) {
         (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
       return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
                        DAG.getNode(ISD::CARRY_FALSE,
-                                   N->getDebugLoc(), EVT::Flag));
+                                   N->getDebugLoc(), MVT::Flag));
   }
 
   return SDValue();
@@ -1878,7 +1878,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
         LN0->isUnindexed() && N0.hasOneUse() &&
         // Do not change the width of a volatile load.
         !LN0->isVolatile()) {
-      EVT ExtVT = EVT::Other;
+      EVT ExtVT = MVT::Other;
       uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
       if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
         ExtVT = EVT::getIntegerVT(ActiveBits);
@@ -1887,7 +1887,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
 
       // Do not generate loads of non-round integer types since these can
       // be expensive (and would be wrong if the type is not byte sized).
-      if (ExtVT != EVT::Other && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
+      if (ExtVT != MVT::Other && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
           (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
         EVT PtrType = N0.getOperand(1).getValueType();
 
@@ -2289,7 +2289,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
   }
 
   // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
-  if (N1C && N1C->getAPIntValue() == 1 && VT == EVT::i1 &&
+  if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
       (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
     SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
     if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
@@ -2793,11 +2793,11 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
   if (N0C && N0C->isNullValue())
     return N2;
   // fold (select C, 1, X) -> (or C, X)
-  if (VT == EVT::i1 && N1C && N1C->getAPIntValue() == 1)
+  if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
     return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
   // fold (select C, 0, 1) -> (xor C, 1)
   if (VT.isInteger() &&
-      (VT0 == EVT::i1 ||
+      (VT0 == MVT::i1 ||
        (VT0.isInteger() &&
         TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
       N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
@@ -2813,27 +2813,27 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
     return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
   }
   // fold (select C, 0, X) -> (and (not C), X)
-  if (VT == VT0 && VT == EVT::i1 && N1C && N1C->isNullValue()) {
+  if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
     SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
     AddToWorkList(NOTNode.getNode());
     return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
   }
   // fold (select C, X, 1) -> (or (not C), X)
-  if (VT == VT0 && VT == EVT::i1 && N2C && N2C->getAPIntValue() == 1) {
+  if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
     SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
     AddToWorkList(NOTNode.getNode());
     return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
   }
   // fold (select C, X, 0) -> (and C, X)
-  if (VT == EVT::i1 && N2C && N2C->isNullValue())
+  if (VT == MVT::i1 && N2C && N2C->isNullValue())
     return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
   // fold (select X, X, Y) -> (or X, Y)
   // fold (select X, 1, Y) -> (or X, Y)
-  if (VT == EVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
+  if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
     return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
   // fold (select X, Y, X) -> (and X, Y)
   // fold (select X, Y, 0) -> (and X, Y)
-  if (VT == EVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
+  if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
     return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
 
   // If we can fold this based on the true/false value, do so.
@@ -2843,10 +2843,10 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
   // fold selects based on a setcc into other things, such as min/max/abs
   if (N0.getOpcode() == ISD::SETCC) {
     // FIXME:
-    // Check against EVT::Other for SELECT_CC, which is a workaround for targets
+    // Check against MVT::Other for SELECT_CC, which is a workaround for targets
     // having to say they don't support SELECT_CC on every type the DAG knows
     // about, since there is no way to mark an opcode illegal at all value types
-    if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, EVT::Other) &&
+    if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
         TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
       return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
                          N0.getOperand(0), N0.getOperand(1),
@@ -3887,7 +3887,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
   if (SrcEltVT.isFloatingPoint()) {
     // Convert the input float vector to a int vector where the elements are the
     // same sizes.
-    assert((SrcEltVT == EVT::f32 || SrcEltVT == EVT::f64) && "Unknown FP VT!");
+    assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
     EVT IntVT = EVT::getIntegerVT(SrcEltVT.getSizeInBits());
     BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
     SrcEltVT = IntVT;
@@ -3896,7 +3896,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
   // Now we know the input is an integer vector.  If the output is a FP type,
   // convert to integer first, then to FP of the right size.
   if (DstEltVT.isFloatingPoint()) {
-    assert((DstEltVT == EVT::f32 || DstEltVT == EVT::f64) && "Unknown FP VT!");
+    assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
     EVT TmpVT = EVT::getIntegerVT(DstEltVT.getSizeInBits());
     SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
 
@@ -3988,7 +3988,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) {
   }
 
   // fold (fadd c1, c2) -> (fadd c1, c2)
-  if (N0CFP && N1CFP && VT != EVT::ppcf128)
+  if (N0CFP && N1CFP && VT != MVT::ppcf128)
     return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
   // canonicalize constant to RHS
   if (N0CFP && !N1CFP)
@@ -4029,7 +4029,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {
   }
 
   // fold (fsub c1, c2) -> c1-c2
-  if (N0CFP && N1CFP && VT != EVT::ppcf128)
+  if (N0CFP && N1CFP && VT != MVT::ppcf128)
     return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
   // fold (fsub A, 0) -> A
   if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
@@ -4063,7 +4063,7 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) {
   }
 
   // fold (fmul c1, c2) -> c1*c2
-  if (N0CFP && N1CFP && VT != EVT::ppcf128)
+  if (N0CFP && N1CFP && VT != MVT::ppcf128)
     return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
   // canonicalize constant to RHS
   if (N0CFP && !N1CFP)
@@ -4118,7 +4118,7 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) {
   }
 
   // fold (fdiv c1, c2) -> c1/c2
-  if (N0CFP && N1CFP && VT != EVT::ppcf128)
+  if (N0CFP && N1CFP && VT != MVT::ppcf128)
     return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
 
 
@@ -4145,7 +4145,7 @@ SDValue DAGCombiner::visitFREM(SDNode *N) {
   EVT VT = N->getValueType(0);
 
   // fold (frem c1, c2) -> fmod(c1,c2)
-  if (N0CFP && N1CFP && VT != EVT::ppcf128)
+  if (N0CFP && N1CFP && VT != MVT::ppcf128)
     return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
 
   return SDValue();
@@ -4158,7 +4158,7 @@ SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
   ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
   EVT VT = N->getValueType(0);
 
-  if (N0CFP && N1CFP && VT != EVT::ppcf128)  // Constant fold
+  if (N0CFP && N1CFP && VT != MVT::ppcf128)  // Constant fold
     return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
 
   if (N1CFP) {
@@ -4208,7 +4208,7 @@ SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
   EVT OpVT = N0.getValueType();
 
   // fold (sint_to_fp c1) -> c1fp
-  if (N0C && OpVT != EVT::ppcf128)
+  if (N0C && OpVT != MVT::ppcf128)
     return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
 
   // If the input is a legal type, and SINT_TO_FP is not legal on this target,
@@ -4230,7 +4230,7 @@ SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
   EVT OpVT = N0.getValueType();
 
   // fold (uint_to_fp c1) -> c1fp
-  if (N0C && OpVT != EVT::ppcf128)
+  if (N0C && OpVT != MVT::ppcf128)
     return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
 
   // If the input is a legal type, and UINT_TO_FP is not legal on this target,
@@ -4263,7 +4263,7 @@ SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
   EVT VT = N->getValueType(0);
 
   // fold (fp_to_uint c1fp) -> c1
-  if (N0CFP && VT != EVT::ppcf128)
+  if (N0CFP && VT != MVT::ppcf128)
     return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
 
   return SDValue();
@@ -4276,7 +4276,7 @@ SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
   EVT VT = N->getValueType(0);
 
   // fold (fp_round c1fp) -> c1fp
-  if (N0CFP && N0.getValueType() != EVT::ppcf128)
+  if (N0CFP && N0.getValueType() != MVT::ppcf128)
     return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
 
   // fold (fp_round (fp_extend x)) -> x
@@ -4330,7 +4330,7 @@ SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
     return SDValue();
 
   // fold (fp_extend c1fp) -> c1fp
-  if (N0CFP && VT != EVT::ppcf128)
+  if (N0CFP && VT != MVT::ppcf128)
     return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
 
   // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
@@ -4398,7 +4398,7 @@ SDValue DAGCombiner::visitFABS(SDNode *N) {
   EVT VT = N->getValueType(0);
 
   // fold (fabs c1) -> fabs(c1)
-  if (N0CFP && VT != EVT::ppcf128)
+  if (N0CFP && VT != MVT::ppcf128)
     return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
   // fold (fabs (fabs x)) -> (fabs x)
   if (N0.getOpcode() == ISD::FABS)
@@ -4438,12 +4438,12 @@ SDValue DAGCombiner::visitBRCOND(SDNode *N) {
     return Chain;
   // unconditional branch
   if (N1C && N1C->getAPIntValue() == 1)
-    return DAG.getNode(ISD::BR, N->getDebugLoc(), EVT::Other, Chain, N2);
+    return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2);
   // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
   // on the target.
   if (N1.getOpcode() == ISD::SETCC &&
-      TLI.isOperationLegalOrCustom(ISD::BR_CC, EVT::Other)) {
-    return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), EVT::Other,
+      TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
+    return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
                        Chain, N1.getOperand(2),
                        N1.getOperand(0), N1.getOperand(1), N2);
   }
@@ -4491,7 +4491,7 @@ SDValue DAGCombiner::visitBRCOND(SDNode *N) {
           removeFromWorkList(N1.getNode());
           DAG.DeleteNode(N1.getNode());
           return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
-                             EVT::Other, Chain, SetCC, N2);
+                             MVT::Other, Chain, SetCC, N2);
         }
       }
     }
@@ -4516,7 +4516,7 @@ SDValue DAGCombiner::visitBR_CC(SDNode *N) {
 
   // fold br_cc true, dest -> br dest (unconditional branch)
   if (SCCC && !SCCC->isNullValue())
-    return DAG.getNode(ISD::BR, N->getDebugLoc(), EVT::Other,
+    return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other,
                        N->getOperand(0), N->getOperand(4));
   // fold br_cc false, dest -> unconditional fall through
   if (SCCC && SCCC->isNullValue())
@@ -4524,7 +4524,7 @@ SDValue DAGCombiner::visitBR_CC(SDNode *N) {
 
   // fold to a simpler setcc
   if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
-    return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), EVT::Other,
+    return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
                        N->getOperand(0), Simp.getOperand(2),
                        Simp.getOperand(0), Simp.getOperand(1),
                        N->getOperand(4));
@@ -4859,7 +4859,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
   // the updated indexed value in case of indexed loads), change uses of the
   // chain value into uses of the chain input (i.e. delete the dead load).
   if (!LD->isVolatile()) {
-    if (N->getValueType(1) == EVT::Other) {
+    if (N->getValueType(1) == MVT::Other) {
       // Unindexed loads.
       if (N->hasNUsesOfValue(0, 0)) {
         // It's not safe to use the two value CombineTo variant here. e.g.
@@ -4883,7 +4883,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
       }
     } else {
       // Indexed loads.
-      assert(N->getValueType(2) == EVT::Other && "Malformed indexed loads?");
+      assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
       if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
         SDValue Undef = DAG.getUNDEF(N->getValueType(0));
         DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
@@ -4942,7 +4942,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
 
       // Create token factor to keep old chain connected.
       SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
-                                  EVT::Other, Chain, ReplLoad.getValue(1));
+                                  MVT::Other, Chain, ReplLoad.getValue(1));
 
       // Replace uses with load result and token factor. Don't add users
       // to work list.
@@ -5096,42 +5096,42 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
     // transform should not be done in this case.
     if (Value.getOpcode() != ISD::TargetConstantFP) {
       SDValue Tmp;
-      switch (CFP->getValueType(0).getSimpleVT()) {
+      switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
       default: llvm_unreachable("Unknown FP type");
-      case EVT::f80:    // We don't do this for these yet.
-      case EVT::f128:
-      case EVT::ppcf128:
+      case MVT::f80:    // We don't do this for these yet.
+      case MVT::f128:
+      case MVT::ppcf128:
         break;
-      case EVT::f32:
-        if (((TLI.isTypeLegal(EVT::i32) || !LegalTypes) && !LegalOperations &&
+      case MVT::f32:
+        if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations &&
              !ST->isVolatile()) ||
-            TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i32)) {
+            TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
           Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
-                              bitcastToAPInt().getZExtValue(), EVT::i32);
+                              bitcastToAPInt().getZExtValue(), MVT::i32);
           return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
                               Ptr, ST->getSrcValue(),
                               ST->getSrcValueOffset(), ST->isVolatile(),
                               ST->getAlignment());
         }
         break;
-      case EVT::f64:
-        if (((TLI.isTypeLegal(EVT::i64) || !LegalTypes) && !LegalOperations &&
+      case MVT::f64:
+        if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations &&
              !ST->isVolatile()) ||
-            TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i64)) {
+            TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
           Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
-                                getZExtValue(), EVT::i64);
+                                getZExtValue(), MVT::i64);
           return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
                               Ptr, ST->getSrcValue(),
                               ST->getSrcValueOffset(), ST->isVolatile(),
                               ST->getAlignment());
         } else if (!ST->isVolatile() &&
-                   TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i32)) {
+                   TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
           // Many FP stores are not made apparent until after legalize, e.g. for
           // argument passing.  Since this is so common, custom legalize the
           // 64-bit integer store into two 32-bit stores.
           uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
-          SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, EVT::i32);
-          SDValue Hi = DAG.getConstant(Val >> 32, EVT::i32);
+          SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
+          SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
           if (TLI.isBigEndian()) std::swap(Lo, Hi);
 
           int SVOffset = ST->getSrcValueOffset();
@@ -5149,7 +5149,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
           SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
                                      Ptr, ST->getSrcValue(),
                                      SVOffset, isVolatile, Alignment);
-          return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), EVT::Other,
+          return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
                              St0, St1);
         }
 
@@ -5179,7 +5179,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
 
       // Create token to keep both nodes around.
       SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
-                                  EVT::Other, Chain, ReplStore);
+                                  MVT::Other, Chain, ReplStore);
 
       // Don't add users to work list.
       return CombineTo(N, Token, false);
@@ -5932,7 +5932,7 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
         Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
                            N2.getValueType(), SCC);
     } else {
-      SCC  = DAG.getSetCC(N0.getDebugLoc(), EVT::i1, N0, N1, CC);
+      SCC  = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
       Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
                          N2.getValueType(), SCC);
     }
@@ -6239,7 +6239,7 @@ SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
   }
 
   // Construct a custom tailored token factor.
-  SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), EVT::Other,
+  SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
                                  &Aliases[0], Aliases.size());
 
   // Make sure the old chain gets cleaned up.
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index f4edc1a30f..cf5b90c900 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -65,10 +65,10 @@ unsigned FastISel::getRegForValue(Value *V) {
   // Ignore illegal types. We must do this before looking up the value
   // in ValueMap because Arguments are given virtual registers regardless
   // of whether FastISel can handle them.
-  EVT::SimpleValueType VT = RealVT.getSimpleVT();
+  MVT VT = RealVT.getSimpleVT();
   if (!TLI.isTypeLegal(VT)) {
-    // Promote EVT::i1 to a legal type though, because it's common and easy.
-    if (VT == EVT::i1)
+    // Promote MVT::i1 to a legal type though, because it's common and easy.
+    if (VT == MVT::i1)
       VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
     else
       return 0;
@@ -190,7 +190,7 @@ unsigned FastISel::getRegForGEPIndex(Value *Idx) {
 ///
 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
   EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
-  if (VT == EVT::Other || !VT.isSimple())
+  if (VT == MVT::Other || !VT.isSimple())
     // Unhandled type. Halt "fast" selection and bail.
     return false;
 
@@ -199,9 +199,9 @@ bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
   // under the assumption that i64 won't be used if the target doesn't
   // support it.
   if (!TLI.isTypeLegal(VT)) {
-    // EVT::i1 is special. Allow AND, OR, or XOR because they
+    // MVT::i1 is special. Allow AND, OR, or XOR because they
     // don't require additional zeroing, which makes them easy.
-    if (VT == EVT::i1 &&
+    if (VT == MVT::i1 &&
         (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
          ISDOpcode == ISD::XOR))
       VT = TLI.getTypeToTransformTo(VT);
@@ -261,7 +261,7 @@ bool FastISel::SelectGetElementPtr(User *I) {
     return false;
 
   const Type *Ty = I->getOperand(0)->getType();
-  EVT::SimpleValueType VT = TLI.getPointerTy();
+  MVT VT = TLI.getPointerTy();
   for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
        OI != E; ++OI) {
     Value *Idx = *OI;
@@ -457,7 +457,7 @@ bool FastISel::SelectCall(User *I) {
     default: break;
     case TargetLowering::Expand: {
       EVT VT = (IID == Intrinsic::eh_selector_i32 ?
-                           EVT::i32 : EVT::i64);
+                           MVT::i32 : MVT::i64);
 
       if (MMI) {
         if (MBB->isLandingPad())
@@ -497,8 +497,8 @@ bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
   EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
   EVT DstVT = TLI.getValueType(I->getType());
     
-  if (SrcVT == EVT::Other || !SrcVT.isSimple() ||
-      DstVT == EVT::Other || !DstVT.isSimple())
+  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
+      DstVT == MVT::Other || !DstVT.isSimple())
     // Unhandled type. Halt "fast" selection and bail.
     return false;
     
@@ -506,7 +506,7 @@ bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
   // it may be i1 if we're doing a truncate because that's
   // easy and somewhat common.
   if (!TLI.isTypeLegal(DstVT))
-    if (DstVT != EVT::i1 || Opcode != ISD::TRUNCATE)
+    if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
       // Unhandled type. Halt "fast" selection and bail.
       return false;
 
@@ -514,7 +514,7 @@ bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
   // it may be i1 if we're doing zero-extension because that's
   // easy and somewhat common.
   if (!TLI.isTypeLegal(SrcVT))
-    if (SrcVT != EVT::i1 || Opcode != ISD::ZERO_EXTEND)
+    if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
       // Unhandled type. Halt "fast" selection and bail.
       return false;
 
@@ -524,14 +524,14 @@ bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
     return false;
 
   // If the operand is i1, arrange for the high bits in the register to be zero.
-  if (SrcVT == EVT::i1) {
+  if (SrcVT == MVT::i1) {
    SrcVT = TLI.getTypeToTransformTo(SrcVT);
    InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
    if (!InputReg)
      return false;
   }
   // If the result is i1, truncate to the target's type for i1 first.
-  if (DstVT == EVT::i1)
+  if (DstVT == MVT::i1)
     DstVT = TLI.getTypeToTransformTo(DstVT);
 
   unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
@@ -559,8 +559,8 @@ bool FastISel::SelectBitCast(User *I) {
   EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
   EVT DstVT = TLI.getValueType(I->getType());
   
-  if (SrcVT == EVT::Other || !SrcVT.isSimple() ||
-      DstVT == EVT::Other || !DstVT.isSimple() ||
+  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
+      DstVT == MVT::Other || !DstVT.isSimple() ||
       !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
     // Unhandled type. Halt "fast" selection and bail.
     return false;
@@ -759,45 +759,44 @@ FastISel::FastISel(MachineFunction &mf,
 
 FastISel::~FastISel() {}
 
-unsigned FastISel::FastEmit_(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_(MVT, MVT,
                              ISD::NodeType) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_r(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_r(MVT, MVT,
                               ISD::NodeType, unsigned /*Op0*/) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_rr(EVT::SimpleValueType, EVT::SimpleValueType, 
+unsigned FastISel::FastEmit_rr(MVT, MVT, 
                                ISD::NodeType, unsigned /*Op0*/,
                                unsigned /*Op0*/) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_i(EVT::SimpleValueType, EVT::SimpleValueType,
-                              ISD::NodeType, uint64_t /*Imm*/) {
+unsigned FastISel::FastEmit_i(MVT, MVT, ISD::NodeType, uint64_t /*Imm*/) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_f(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_f(MVT, MVT,
                               ISD::NodeType, ConstantFP * /*FPImm*/) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_ri(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_ri(MVT, MVT,
                                ISD::NodeType, unsigned /*Op0*/,
                                uint64_t /*Imm*/) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_rf(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_rf(MVT, MVT,
                                ISD::NodeType, unsigned /*Op0*/,
                                ConstantFP * /*FPImm*/) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_rri(EVT::SimpleValueType, EVT::SimpleValueType,
+unsigned FastISel::FastEmit_rri(MVT, MVT,
                                 ISD::NodeType,
                                 unsigned /*Op0*/, unsigned /*Op1*/,
                                 uint64_t /*Imm*/) {
@@ -808,9 +807,9 @@ unsigned FastISel::FastEmit_rri(EVT::SimpleValueType, EVT::SimpleValueType,
 /// to emit an instruction with an immediate operand using FastEmit_ri.
 /// If that fails, it materializes the immediate into a register and try
 /// FastEmit_rr instead.
-unsigned FastISel::FastEmit_ri_(EVT::SimpleValueType VT, ISD::NodeType Opcode,
+unsigned FastISel::FastEmit_ri_(MVT VT, ISD::NodeType Opcode,
                                 unsigned Op0, uint64_t Imm,
-                                EVT::SimpleValueType ImmType) {
+                                MVT ImmType) {
   // First check if immediate type is legal. If not, we can't use the ri form.
   unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
   if (ResultReg != 0)
@@ -825,9 +824,9 @@ unsigned FastISel::FastEmit_ri_(EVT::SimpleValueType VT, ISD::NodeType Opcode,
 /// to emit an instruction with a floating-point immediate operand using
 /// FastEmit_rf. If that fails, it materializes the immediate into a register
 /// and try FastEmit_rr instead.
-unsigned FastISel::FastEmit_rf_(EVT::SimpleValueType VT, ISD::NodeType Opcode,
+unsigned FastISel::FastEmit_rf_(MVT VT, ISD::NodeType Opcode,
                                 unsigned Op0, ConstantFP *FPImm,
-                                EVT::SimpleValueType ImmType) {
+                                MVT ImmType) {
   // First check if immediate type is legal. If not, we can't use the rf form.
   unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
   if (ResultReg != 0)
@@ -988,7 +987,7 @@ unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
   return ResultReg;
 }
 
-unsigned FastISel::FastEmitInst_extractsubreg(EVT::SimpleValueType RetVT,
+unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
                                               unsigned Op0, uint32_t Idx) {
   const TargetRegisterClass* RC = MRI.getRegClass(Op0);
   
@@ -1009,6 +1008,6 @@ unsigned FastISel::FastEmitInst_extractsubreg(EVT::SimpleValueType RetVT,
 
 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
 /// with all but the least significant bit set to zero.
-unsigned FastISel::FastEmitZExtFromI1(EVT::SimpleValueType VT, unsigned Op) {
+unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) {
   return FastEmit_ri(VT, VT, ISD::AND, Op, 1);
 }
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index de445ed261..cc63de3774 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -213,7 +213,7 @@ SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
                                            CodeGenOpt::Level ol)
   : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
     ValueTypeActions(TLI.getValueTypeActions()) {
-  assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE &&
+  assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
          "Too many value types for ValueTypeActions to hold!");
 }
 
@@ -254,19 +254,19 @@ static SDNode *FindCallEndFromCallStart(SDNode *Node) {
 
   // The chain is usually at the end.
   SDValue TheChain(Node, Node->getNumValues()-1);
-  if (TheChain.getValueType() != EVT::Other) {
+  if (TheChain.getValueType() != MVT::Other) {
     // Sometimes it's at the beginning.
     TheChain = SDValue(Node, 0);
-    if (TheChain.getValueType() != EVT::Other) {
+    if (TheChain.getValueType() != MVT::Other) {
       // Otherwise, hunt for it.
       for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
-        if (Node->getValueType(i) == EVT::Other) {
+        if (Node->getValueType(i) == MVT::Other) {
           TheChain = SDValue(Node, i);
           break;
         }
 
       // Otherwise, we walked into a node without a chain.
-      if (TheChain.getValueType() != EVT::Other)
+      if (TheChain.getValueType() != MVT::Other)
         return 0;
     }
   }
@@ -290,7 +290,7 @@ static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
   assert(Node && "Didn't find callseq_start for a call??");
   if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
 
-  assert(Node->getOperand(0).getValueType() == EVT::Other &&
+  assert(Node->getOperand(0).getValueType() == MVT::Other &&
          "Node doesn't have a token chain argument!");
   return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
 }
@@ -347,15 +347,15 @@ static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
   EVT VT = CFP->getValueType(0);
   ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
   if (!UseCP) {
-    assert((VT == EVT::f64 || VT == EVT::f32) && "Invalid type expansion");
+    assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
     return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
-                           (VT == EVT::f64) ? EVT::i64 : EVT::i32);
+                           (VT == MVT::f64) ? MVT::i64 : MVT::i32);
   }
 
   EVT OrigVT = VT;
   EVT SVT = VT;
-  while (SVT != EVT::f32) {
-    SVT = (EVT::SimpleValueType)(SVT.getSimpleVT() - 1);
+  while (SVT != MVT::f32) {
+    SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
     if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
         // Only do this if the target has a native EXTLOAD instruction from
         // smaller type.
@@ -450,7 +450,7 @@ SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
                                          MemVT, ST->isVolatile(),
                                          MinAlign(ST->getAlignment(), Offset)));
       // The order of the stores doesn't matter - say it with a TokenFactor.
-      return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Stores[0],
+      return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
                          Stores.size());
     }
   }
@@ -459,7 +459,7 @@ SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
          "Unaligned store of unknown type.");
   // Get the half-size VT
   EVT NewStoredVT =
-    (EVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
+    (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT().SimpleTy - 1);
   int NumBits = NewStoredVT.getSizeInBits();
   int IncrementSize = NumBits / 8;
 
@@ -480,7 +480,7 @@ SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
                              ST->getSrcValue(), SVOffset + IncrementSize,
                              NewStoredVT, ST->isVolatile(), Alignment);
 
-  return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Store1, Store2);
+  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
 }
 
 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
@@ -552,7 +552,7 @@ SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
                                          NULL, 0, MemVT));
 
       // The order of the stores doesn't matter - say it with a TokenFactor.
-      SDValue TF = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Stores[0],
+      SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
                                Stores.size());
 
       // Finally, perform the original load only redirected to the stack slot.
@@ -607,7 +607,7 @@ SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
   SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
   Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
 
-  SDValue TF = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+  SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
                              Hi.getValue(1));
 
   SDValue Ops[] = { Result, TF };
@@ -702,27 +702,27 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
   bool isVolatile = ST->isVolatile();
   DebugLoc dl = ST->getDebugLoc();
   if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
-    if (CFP->getValueType(0) == EVT::f32 &&
-        getTypeAction(EVT::i32) == Legal) {
+    if (CFP->getValueType(0) == MVT::f32 &&
+        getTypeAction(MVT::i32) == Legal) {
       Tmp3 = DAG.getConstant(CFP->getValueAPF().
                                       bitcastToAPInt().zextOrTrunc(32),
-                              EVT::i32);
+                              MVT::i32);
       return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
                           SVOffset, isVolatile, Alignment);
-    } else if (CFP->getValueType(0) == EVT::f64) {
+    } else if (CFP->getValueType(0) == MVT::f64) {
       // If this target supports 64-bit registers, do a single 64-bit store.
-      if (getTypeAction(EVT::i64) == Legal) {
+      if (getTypeAction(MVT::i64) == Legal) {
         Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
-                                  zextOrTrunc(64), EVT::i64);
+                                  zextOrTrunc(64), MVT::i64);
         return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
                             SVOffset, isVolatile, Alignment);
-      } else if (getTypeAction(EVT::i32) == Legal && !ST->isVolatile()) {
+      } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
         // Otherwise, if the target supports 32-bit registers, use 2 32-bit
         // stores.  If the target supports neither 32- nor 64-bits, this
         // xform is certainly not worth it.
         const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
-        SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), EVT::i32);
-        SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), EVT::i32);
+        SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
+        SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
         if (TLI.isBigEndian()) std::swap(Lo, Hi);
 
         Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
@@ -732,7 +732,7 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
         Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
                           isVolatile, MinAlign(Alignment, 4U));
 
-        return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+        return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
       }
     }
   }
@@ -777,7 +777,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
   case ISD::INTRINSIC_VOID:
   case ISD::VAARG:
   case ISD::STACKSAVE:
-    Action = TLI.getOperationAction(Node->getOpcode(), EVT::Other);
+    Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
     break;
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP:
@@ -882,7 +882,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     case ISD::BR_CC:
     case ISD::BRCOND:
       // Branches tweak the chain to include LastCALLSEQ_END
-      Ops[0] = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Ops[0],
+      Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
                             LastCALLSEQ_END);
       Ops[0] = LegalizeOp(Ops[0]);
       LastCALLSEQ_END = DAG.getEntryNode();
@@ -979,7 +979,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     // Merge in the last call, to ensure that this call start after the last
     // call ended.
     if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
-      Tmp1 = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+      Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
                          Tmp1, LastCALLSEQ_END);
       Tmp1 = LegalizeOp(Tmp1);
     }
@@ -1026,7 +1026,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
     // Do not try to legalize the target-specific arguments (#1+), except for
     // an optional flag input.
-    if (Node->getOperand(Node->getNumOperands()-1).getValueType() != EVT::Flag){
+    if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
       if (Tmp1 != Node->getOperand(0)) {
         SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
         Ops[0] = Tmp1;
@@ -1122,8 +1122,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           // tells the optimizers that those bits are undefined.  It would be
           // nice to have an effective generic way of getting these benefits...
           // Until such a way is found, don't insist on promoting i1 here.
-          (SrcVT != EVT::i1 ||
-           TLI.getLoadExtAction(ExtType, EVT::i1) == TargetLowering::Promote)) {
+          (SrcVT != MVT::i1 ||
+           TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
         // Promote to a byte-sized load if not loading an integral number of
         // bytes.  For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
         unsigned NewWidth = SrcVT.getStoreSizeInBits();
@@ -1189,7 +1189,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
 
           // Build a factor node to remember that this load is independent of the
           // other one.
-          Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+          Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
                            Hi.getValue(1));
 
           // Move the top bits to the right place.
@@ -1218,7 +1218,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
 
           // Build a factor node to remember that this load is independent of the
           // other one.
-          Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+          Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
                            Hi.getValue(1));
 
           // Move the top bits to the right place.
@@ -1267,7 +1267,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           break;
         case TargetLowering::Expand:
           // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
-          if (SrcVT == EVT::f32 && Node->getValueType(0) == EVT::f64) {
+          if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
             SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
                                          LD->getSrcValueOffset(),
                                          LD->isVolatile(), LD->getAlignment());
@@ -1416,7 +1416,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         }
 
         // The order of the stores doesn't matter.
-        Result = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+        Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
       } else {
         if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
             Tmp2 != ST->getBasePtr())
@@ -1524,7 +1524,7 @@ SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
 
   SDValue StoreChain;
   if (!Stores.empty())    // Not all undef elements?
-    StoreChain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+    StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
                              &Stores[0], Stores.size());
   else
     StoreChain = DAG.getEntryNode();
@@ -1537,28 +1537,28 @@ SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
   DebugLoc dl = Node->getDebugLoc();
   SDValue Tmp1 = Node->getOperand(0);
   SDValue Tmp2 = Node->getOperand(1);
-  assert((Tmp2.getValueType() == EVT::f32 ||
-          Tmp2.getValueType() == EVT::f64) &&
+  assert((Tmp2.getValueType() == MVT::f32 ||
+          Tmp2.getValueType() == MVT::f64) &&
           "Ugly special-cased code!");
   // Get the sign bit of the RHS.
   SDValue SignBit;
-  EVT IVT = Tmp2.getValueType() == EVT::f64 ? EVT::i64 : EVT::i32;
+  EVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32;
   if (isTypeLegal(IVT)) {
     SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
   } else {
     assert(isTypeLegal(TLI.getPointerTy()) &&
-            (TLI.getPointerTy() == EVT::i32 || 
-            TLI.getPointerTy() == EVT::i64) &&
+            (TLI.getPointerTy() == MVT::i32 || 
+            TLI.getPointerTy() == MVT::i64) &&
             "Legal type for load?!");
     SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType());
     SDValue StorePtr = StackPtr, LoadPtr = StackPtr;
     SDValue Ch =
         DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0);
-    if (Tmp2.getValueType() == EVT::f64 && TLI.isLittleEndian())
+    if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian())
       LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(),
                             LoadPtr, DAG.getIntPtrConstant(4));
     SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(),
-                              Ch, LoadPtr, NULL, 0, EVT::i32);
+                              Ch, LoadPtr, NULL, 0, MVT::i32);
   }
   SignBit =
       DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
@@ -1577,8 +1577,8 @@ SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) {
   DebugLoc dl = Node->getDebugLoc();
   DwarfWriter *DW = DAG.getDwarfWriter();
   bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
-                                                    EVT::Other);
-  bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, EVT::Other);
+                                                    MVT::Other);
+  bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
 
   const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
   GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
@@ -1592,9 +1592,9 @@ SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) {
       // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
       // won't hurt anything.
       if (useDEBUG_LOC) {
-        return DAG.getNode(ISD::DEBUG_LOC, dl, EVT::Other, Node->getOperand(0),
-                           DAG.getConstant(Line, EVT::i32),
-                           DAG.getConstant(Col, EVT::i32),
+        return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0),
+                           DAG.getConstant(Line, MVT::i32),
+                           DAG.getConstant(Col, MVT::i32),
                            DAG.getSrcValue(CU.getGV()));
       } else {
         unsigned ID = DW->RecordSourceLine(Line, Col, CU);
@@ -1886,12 +1886,12 @@ SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
                                               RTLIB::Libcall Call_F80,
                                               RTLIB::Libcall Call_PPCF128) {
   RTLIB::Libcall LC;
-  switch (Node->getValueType(0).getSimpleVT()) {
+  switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
   default: llvm_unreachable("Unexpected request for libcall!");
-  case EVT::f32: LC = Call_F32; break;
-  case EVT::f64: LC = Call_F64; break;
-  case EVT::f80: LC = Call_F80; break;
-  case EVT::ppcf128: LC = Call_PPCF128; break;
+  case MVT::f32: LC = Call_F32; break;
+  case MVT::f64: LC = Call_F64; break;
+  case MVT::f80: LC = Call_F80; break;
+  case MVT::ppcf128: LC = Call_PPCF128; break;
   }
   return ExpandLibCall(LC, Node, false);
 }
@@ -1902,12 +1902,12 @@ SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
                                                RTLIB::Libcall Call_I64,
                                                RTLIB::Libcall Call_I128) {
   RTLIB::Libcall LC;
-  switch (Node->getValueType(0).getSimpleVT()) {
+  switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
   default: llvm_unreachable("Unexpected request for libcall!");
-  case EVT::i16: LC = Call_I16; break;
-  case EVT::i32: LC = Call_I32; break;
-  case EVT::i64: LC = Call_I64; break;
-  case EVT::i128: LC = Call_I128; break;
+  case MVT::i16: LC = Call_I16; break;
+  case MVT::i32: LC = Call_I32; break;
+  case MVT::i64: LC = Call_I64; break;
+  case MVT::i128: LC = Call_I128; break;
   }
   return ExpandLibCall(LC, Node, isSigned);
 }
@@ -1920,11 +1920,11 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
                                                    SDValue Op0,
                                                    EVT DestVT,
                                                    DebugLoc dl) {
-  if (Op0.getValueType() == EVT::i32) {
+  if (Op0.getValueType() == MVT::i32) {
     // simple 32-bit [signed|unsigned] integer to float/double expansion
 
     // Get the stack frame index of a 8 byte buffer.
-    SDValue StackSlot = DAG.CreateStackTemporary(EVT::f64);
+    SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
 
     // word offset constant for Hi/Lo address computation
     SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
@@ -1939,8 +1939,8 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
     SDValue Op0Mapped;
     if (isSigned) {
       // constant used to invert sign bit (signed to unsigned mapping)
-      SDValue SignBit = DAG.getConstant(0x80000000u, EVT::i32);
-      Op0Mapped = DAG.getNode(ISD::XOR, dl, EVT::i32, Op0, SignBit);
+      SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
+      Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
     } else {
       Op0Mapped = Op0;
     }
@@ -1948,28 +1948,28 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
     SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
                                   Op0Mapped, Lo, NULL, 0);
     // initial hi portion of constructed double
-    SDValue InitialHi = DAG.getConstant(0x43300000u, EVT::i32);
+    SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
     // store the hi of the constructed double - biased exponent
     SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
     // load the constructed double
-    SDValue Load = DAG.getLoad(EVT::f64, dl, Store2, StackSlot, NULL, 0);
+    SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
     // FP constant to bias correct the final result
     SDValue Bias = DAG.getConstantFP(isSigned ?
                                      BitsToDouble(0x4330000080000000ULL) :
                                      BitsToDouble(0x4330000000000000ULL),
-                                     EVT::f64);
+                                     MVT::f64);
     // subtract the bias
-    SDValue Sub = DAG.getNode(ISD::FSUB, dl, EVT::f64, Load, Bias);
+    SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
     // final result
     SDValue Result;
     // handle final rounding
-    if (DestVT == EVT::f64) {
+    if (DestVT == MVT::f64) {
       // do nothing
       Result = Sub;
-    } else if (DestVT.bitsLT(EVT::f64)) {
+    } else if (DestVT.bitsLT(MVT::f64)) {
       Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
                            DAG.getIntPtrConstant(0));
-    } else if (DestVT.bitsGT(EVT::f64)) {
+    } else if (DestVT.bitsGT(MVT::f64)) {
       Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
     }
     return Result;
@@ -1988,12 +1988,12 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
   // as a negative number.  To counteract this, the dynamic code adds an
   // offset depending on the data type.
   uint64_t FF;
-  switch (Op0.getValueType().getSimpleVT()) {
+  switch (Op0.getValueType().getSimpleVT().SimpleTy) {
   default: llvm_unreachable("Unsupported integer type!");
-  case EVT::i8 : FF = 0x43800000ULL; break;  // 2^8  (as a float)
-  case EVT::i16: FF = 0x47800000ULL; break;  // 2^16 (as a float)
-  case EVT::i32: FF = 0x4F800000ULL; break;  // 2^32 (as a float)
-  case EVT::i64: FF = 0x5F800000ULL; break;  // 2^64 (as a float)
+  case MVT::i8 : FF = 0x43800000ULL; break;  // 2^8  (as a float)
+  case MVT::i16: FF = 0x47800000ULL; break;  // 2^16 (as a float)
+  case MVT::i32: FF = 0x4F800000ULL; break;  // 2^32 (as a float)
+  case MVT::i64: FF = 0x5F800000ULL; break;  // 2^64 (as a float)
   }
   if (TLI.isLittleEndian()) FF <<= 32;
   Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
@@ -2003,8 +2003,8 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
   CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
   Alignment = std::min(Alignment, 4u);
   SDValue FudgeInReg;
-  if (DestVT == EVT::f32)
-    FudgeInReg = DAG.getLoad(EVT::f32, dl, DAG.getEntryNode(), CPIdx,
+  if (DestVT == MVT::f32)
+    FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
                              PseudoSourceValue::getConstantPool(), 0,
                              false, Alignment);
   else {
@@ -2012,7 +2012,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
       LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
                                 DAG.getEntryNode(), CPIdx,
                                 PseudoSourceValue::getConstantPool(), 0,
-                                EVT::f32, false, Alignment));
+                                MVT::f32, false, Alignment));
   }
 
   return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
@@ -2034,7 +2034,7 @@ SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
 
   // Scan for the appropriate larger type to use.
   while (1) {
-    NewInTy = (EVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
+    NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
     assert(NewInTy.isInteger() && "Ran out of possibilities!");
 
     // If the target supports SINT_TO_FP of this type, use it.
@@ -2076,7 +2076,7 @@ SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
 
   // Scan for the appropriate larger type to use.
   while (1) {
-    NewOutTy = (EVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
+    NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
     assert(NewOutTy.isInteger() && "Ran out of possibilities!");
 
     if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
@@ -2107,13 +2107,13 @@ SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
   EVT VT = Op.getValueType();
   EVT SHVT = TLI.getShiftAmountTy();
   SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
-  switch (VT.getSimpleVT()) {
+  switch (VT.getSimpleVT().SimpleTy) {
   default: llvm_unreachable("Unhandled Expand type in BSWAP!");
-  case EVT::i16:
+  case MVT::i16:
     Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
     Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
     return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
-  case EVT::i32:
+  case MVT::i32:
     Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
     Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
     Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
@@ -2123,7 +2123,7 @@ SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
     Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
     Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
     return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
-  case EVT::i64:
+  case MVT::i64:
     Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
     Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
     Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
@@ -2834,7 +2834,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
       Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
                           TLI.getPICJumpTableRelocBase(Table, DAG));
     }
-    Tmp1 = DAG.getNode(ISD::BRIND, dl, EVT::Other, LD.getValue(1), Addr);
+    Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
     Results.push_back(Tmp1);
     break;
   }
@@ -2844,12 +2844,12 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
     Tmp1 = Node->getOperand(0);
     Tmp2 = Node->getOperand(1);
     if (Tmp2.getOpcode() == ISD::SETCC) {
-      Tmp1 = DAG.getNode(ISD::BR_CC, dl, EVT::Other,
+      Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
                          Tmp1, Tmp2.getOperand(2),
                          Tmp2.getOperand(0), Tmp2.getOperand(1),
                          Node->getOperand(2));
     } else {
-      Tmp1 = DAG.getNode(ISD::BR_CC, dl, EVT::Other, Tmp1,
+      Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
                          DAG.getCondCode(ISD::SETNE), Tmp2,
                          DAG.getConstant(0, Tmp2.getValueType()),
                          Node->getOperand(2));
diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index ebaf2fb4cc..95927a0f9b 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -31,10 +31,10 @@ static RTLIB::Libcall GetFPLibCall(EVT VT,
                                    RTLIB::Libcall Call_F80,
                                    RTLIB::Libcall Call_PPCF128) {
   return
-    VT == EVT::f32 ? Call_F32 :
-    VT == EVT::f64 ? Call_F64 :
-    VT == EVT::f80 ? Call_F80 :
-    VT == EVT::ppcf128 ? Call_PPCF128 :
+    VT == MVT::f32 ? Call_F32 :
+    VT == MVT::f64 ? Call_F64 :
+    VT == MVT::f80 ? Call_F80 :
+    VT == MVT::ppcf128 ? Call_PPCF128 :
     RTLIB::UNKNOWN_LIBCALL;
 }
 
@@ -353,7 +353,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FPOW(SDNode *N) {
 }
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
-  assert(N->getOperand(1).getValueType() == EVT::i32 &&
+  assert(N->getOperand(1).getValueType() == MVT::i32 &&
          "Unsupported power type!");
   EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
   SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), N->getOperand(1) };
@@ -510,9 +510,9 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_XINT_TO_FP(SDNode *N) {
   // a larger type, eg: i8 -> fp.  Even if it is legal, no libcall may exactly
   // match.  Look for an appropriate libcall.
   RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
-  for (unsigned t = EVT::FIRST_INTEGER_VALUETYPE;
-       t <= EVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
-    NVT = (EVT::SimpleValueType)t;
+  for (unsigned t = MVT::FIRST_INTEGER_VALUETYPE;
+       t <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
+    NVT = (MVT::SimpleValueType)t;
     // The source needs to big enough to hold the operand.
     if (NVT.bitsGE(SVT))
       LC = Signed ? RTLIB::getSINTTOFP(NVT, RVT):RTLIB::getUINTTOFP (NVT, RVT);
@@ -576,68 +576,68 @@ void DAGTypeLegalizer::SoftenSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
   SDValue RHSInt = GetSoftenedFloat(NewRHS);
   EVT VT = NewLHS.getValueType();
 
-  assert((VT == EVT::f32 || VT == EVT::f64) && "Unsupported setcc type!");
+  assert((VT == MVT::f32 || VT == MVT::f64) && "Unsupported setcc type!");
 
   // Expand into one or more soft-fp libcall(s).
   RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
   switch (CCCode) {
   case ISD::SETEQ:
   case ISD::SETOEQ:
-    LC1 = (VT == EVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
+    LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
     break;
   case ISD::SETNE:
   case ISD::SETUNE:
-    LC1 = (VT == EVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
+    LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
     break;
   case ISD::SETGE:
   case ISD::SETOGE:
-    LC1 = (VT == EVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
+    LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
     break;
   case ISD::SETLT:
   case ISD::SETOLT:
-    LC1 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
+    LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
     break;
   case ISD::SETLE:
   case ISD::SETOLE:
-    LC1 = (VT == EVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
+    LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
     break;
   case ISD::SETGT:
   case ISD::SETOGT:
-    LC1 = (VT == EVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
+    LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
     break;
   case ISD::SETUO:
-    LC1 = (VT == EVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
+    LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
     break;
   case ISD::SETO:
-    LC1 = (VT == EVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
+    LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
     break;
   default:
-    LC1 = (VT == EVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
+    LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
     switch (CCCode) {
     case ISD::SETONE:
       // SETONE = SETOLT | SETOGT
-      LC1 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
+      LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
       // Fallthrough
     case ISD::SETUGT:
-      LC2 = (VT == EVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
+      LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
       break;
     case ISD::SETUGE:
-      LC2 = (VT == EVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
+      LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
       break;
     case ISD::SETULT:
-      LC2 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
+      LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
       break;
     case ISD::SETULE:
-      LC2 = (VT == EVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
+      LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
       break;
     case ISD::SETUEQ:
-      LC2 = (VT == EVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
+      LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
       break;
     default: assert(false && "Do not know how to soften this setcc!");
     }
   }
 
-  EVT RetVT = EVT::i32; // FIXME: is this the correct return type?
+  EVT RetVT = MVT::i32; // FIXME: is this the correct return type?
   SDValue Ops[2] = { LHSInt, RHSInt };
   NewLHS = MakeLibCall(LC1, RetVT, Ops, 2, false/*sign irrelevant*/, dl);
   NewRHS = DAG.getConstant(0, RetVT);
@@ -841,7 +841,7 @@ void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo,
 
 void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo,
                                            SDValue &Hi) {
-  assert(N->getValueType(0) == EVT::ppcf128 &&
+  assert(N->getValueType(0) == MVT::ppcf128 &&
          "Logic only correct for ppcf128!");
   DebugLoc dl = N->getDebugLoc();
   SDValue Tmp;
@@ -1088,7 +1088,7 @@ void DAGTypeLegalizer::ExpandFloatRes_LOAD(SDNode *N, SDValue &Lo,
 
 void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
                                                  SDValue &Hi) {
-  assert(N->getValueType(0) == EVT::ppcf128 && "Unsupported XINT_TO_FP!");
+  assert(N->getValueType(0) == MVT::ppcf128 && "Unsupported XINT_TO_FP!");
   EVT VT = N->getValueType(0);
   EVT NVT = TLI.getTypeToTransformTo(VT);
   SDValue Src = N->getOperand(0);
@@ -1099,20 +1099,20 @@ void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
   // First do an SINT_TO_FP, whether the original was signed or unsigned.
   // When promoting partial word types to i32 we must honor the signedness,
   // though.
-  if (SrcVT.bitsLE(EVT::i32)) {
+  if (SrcVT.bitsLE(MVT::i32)) {
     // The integer can be represented exactly in an f64.
     Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
-                      EVT::i32, Src);
+                      MVT::i32, Src);
     Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT);
     Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src);
   } else {
     RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
-    if (SrcVT.bitsLE(EVT::i64)) {
+    if (SrcVT.bitsLE(MVT::i64)) {
       Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
-                        EVT::i64, Src);
+                        MVT::i64, Src);
       LC = RTLIB::SINTTOFP_I64_PPCF128;
-    } else if (SrcVT.bitsLE(EVT::i128)) {
-      Src = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i128, Src);
+    } else if (SrcVT.bitsLE(MVT::i128)) {
+      Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src);
       LC = RTLIB::SINTTOFP_I128_PPCF128;
     }
     assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
@@ -1134,23 +1134,23 @@ void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
   static const uint64_t TwoE128[] = { 0x47f0000000000000LL, 0 };
   const uint64_t *Parts = 0;
 
-  switch (SrcVT.getSimpleVT()) {
+  switch (SrcVT.getSimpleVT().SimpleTy) {
   default:
     assert(false && "Unsupported UINT_TO_FP!");
-  case EVT::i32:
+  case MVT::i32:
     Parts = TwoE32;
     break;
-  case EVT::i64:
+  case MVT::i64:
     Parts = TwoE64;
     break;
-  case EVT::i128:
+  case MVT::i128:
     Parts = TwoE128;
     break;
   }
 
   Lo = DAG.getNode(ISD::FADD, dl, VT, Hi,
                    DAG.getConstantFP(APFloat(APInt(128, 2, Parts)),
-                                     EVT::ppcf128));
+                                     MVT::ppcf128));
   Lo = DAG.getNode(ISD::SELECT_CC, dl, VT, Src, DAG.getConstant(0, SrcVT),
                    Lo, Hi, DAG.getCondCode(ISD::SETLT));
   GetPairElements(Lo, Lo, Hi);
@@ -1223,7 +1223,7 @@ void DAGTypeLegalizer::FloatExpandSetCCOperands(SDValue &NewLHS,
   GetExpandedFloat(NewRHS, RHSLo, RHSHi);
 
   EVT VT = NewLHS.getValueType();
-  assert(VT == EVT::ppcf128 && "Unsupported setcc type!");
+  assert(VT == MVT::ppcf128 && "Unsupported setcc type!");
 
   // FIXME:  This generated code sucks.  We want to generate
   //         FCMPU crN, hi1, hi2
@@ -1264,7 +1264,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_BR_CC(SDNode *N) {
 }
 
 SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
-  assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
+  assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
          "Logic only correct for ppcf128!");
   SDValue Lo, Hi;
   GetExpandedFloat(N->getOperand(0), Lo, Hi);
@@ -1279,14 +1279,14 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) {
 
   // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
   // PPC (the libcall is not available).  FIXME: Do this in a less hacky way.
-  if (RVT == EVT::i32) {
-    assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
+  if (RVT == MVT::i32) {
+    assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
            "Logic only correct for ppcf128!");
-    SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, EVT::ppcf128,
-                              N->getOperand(0), DAG.getValueType(EVT::f64));
-    Res = DAG.getNode(ISD::FP_ROUND, dl, EVT::f64, Res,
+    SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
+                              N->getOperand(0), DAG.getValueType(MVT::f64));
+    Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res,
                       DAG.getIntPtrConstant(1));
-    return DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, Res);
+    return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res);
   }
 
   RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT);
@@ -1300,24 +1300,24 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) {
 
   // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
   // PPC (the libcall is not available).  FIXME: Do this in a less hacky way.
-  if (RVT == EVT::i32) {
-    assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
+  if (RVT == MVT::i32) {
+    assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
            "Logic only correct for ppcf128!");
     const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
     APFloat APF = APFloat(APInt(128, 2, TwoE31));
-    SDValue Tmp = DAG.getConstantFP(APF, EVT::ppcf128);
+    SDValue Tmp = DAG.getConstantFP(APF, MVT::ppcf128);
     //  X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
     // FIXME: generated code sucks.
-    return DAG.getNode(ISD::SELECT_CC, dl, EVT::i32, N->getOperand(0), Tmp,
-                       DAG.getNode(ISD::ADD, dl, EVT::i32,
-                                   DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32,
+    return DAG.getNode(ISD::SELECT_CC, dl, MVT::i32, N->getOperand(0), Tmp,
+                       DAG.getNode(ISD::ADD, dl, MVT::i32,
+                                   DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32,
                                                DAG.getNode(ISD::FSUB, dl,
-                                                           EVT::ppcf128,
+                                                           MVT::ppcf128,
                                                            N->getOperand(0),
                                                            Tmp)),
-                                   DAG.getConstant(0x80000000, EVT::i32)),
+                                   DAG.getConstant(0x80000000, MVT::i32)),
                        DAG.getNode(ISD::FP_TO_SINT, dl,
-                                   EVT::i32, N->getOperand(0)),
+                                   MVT::i32, N->getOperand(0)),
                        DAG.getCondCode(ISD::SETGE));
   }
 
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index b1b2ae3e5c..3d71432593 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -718,7 +718,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
   assert(OpNo == 1 && "only know how to promote condition");
 
   // Promote all the way up to the canonical SetCC type.
-  EVT SVT = TLI.getSetCCResultType(EVT::Other);
+  EVT SVT = TLI.getSetCCResultType(MVT::Other);
   SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
 
   // The chain (Op#0) and basic block destination (Op#2) are always legal types.
@@ -802,7 +802,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
   NewOps[0] = N->getOperand(0);
   for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
     SDValue Flag = GetPromotedInteger(N->getOperand(i));
-    NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, EVT::i1);
+    NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
   }
   return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
                                 array_lengthof(NewOps));
@@ -1009,7 +1009,7 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
                TLI.isOperationLegalOrCustom(ISD::ADDC,
                                             TLI.getTypeToExpandTo(NVT))) {
       // Emit this X << 1 as X+X.
-      SDVTList VTList = DAG.getVTList(NVT, EVT::Flag);
+      SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
       SDValue LoOps[2] = { InL, InL };
       Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
       SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
@@ -1237,7 +1237,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
   // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
   // them.  TODO: Teach operation legalization how to expand unsupported
   // ADDC/ADDE/SUBC/SUBE.  The problem is that these operations generate
-  // a carry of type EVT::Flag, but there doesn't seem to be any way to
+  // a carry of type MVT::Flag, but there doesn't seem to be any way to
   // generate a value of this type in the expanded code sequence.
   bool hasCarry =
     TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
@@ -1245,7 +1245,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
                                  TLI.getTypeToExpandTo(NVT));
 
   if (hasCarry) {
-    SDVTList VTList = DAG.getVTList(NVT, EVT::Flag);
+    SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
     if (N->getOpcode() == ISD::ADD) {
       Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
       HiOps[2] = Lo.getValue(1);
@@ -1290,7 +1290,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
   DebugLoc dl = N->getDebugLoc();
   GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
   GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
-  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), EVT::Flag);
+  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
   SDValue LoOps[2] = { LHSL, RHSL };
   SDValue HiOps[3] = { LHSH, RHSH };
 
@@ -1316,7 +1316,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
   DebugLoc dl = N->getDebugLoc();
   GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
   GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
-  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), EVT::Flag);
+  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
   SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
   SDValue HiOps[3] = { LHSH, RHSH };
 
@@ -1539,7 +1539,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
 
     // Build a factor node to remember that this load is independent of the
     // other one.
-    Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+    Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
                      Hi.getValue(1));
   } else {
     // Big-endian - high bits are at low addresses.  Favor aligned loads at
@@ -1565,7 +1565,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
 
     // Build a factor node to remember that this load is independent of the
     // other one.
-    Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+    Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
                      Hi.getValue(1));
 
     if (ExcessBits < NVT.getSizeInBits()) {
@@ -1673,13 +1673,13 @@ void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
 
   // If nothing else, we can make a libcall.
   RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
-  if (VT == EVT::i16)
+  if (VT == MVT::i16)
     LC = RTLIB::MUL_I16;
-  else if (VT == EVT::i32)
+  else if (VT == MVT::i32)
     LC = RTLIB::MUL_I32;
-  else if (VT == EVT::i64)
+  else if (VT == MVT::i64)
     LC = RTLIB::MUL_I64;
-  else if (VT == EVT::i128)
+  else if (VT == MVT::i128)
     LC = RTLIB::MUL_I128;
   assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
 
@@ -1693,13 +1693,13 @@ void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
   DebugLoc dl = N->getDebugLoc();
 
   RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
-  if (VT == EVT::i16)
+  if (VT == MVT::i16)
     LC = RTLIB::SDIV_I16;
-  else if (VT == EVT::i32)
+  else if (VT == MVT::i32)
     LC = RTLIB::SDIV_I32;
-  else if (VT == EVT::i64)
+  else if (VT == MVT::i64)
     LC = RTLIB::SDIV_I64;
-  else if (VT == EVT::i128)
+  else if (VT == MVT::i128)
     LC = RTLIB::SDIV_I128;
   assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
 
@@ -1755,34 +1755,34 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
   bool isSigned;
   if (N->getOpcode() == ISD::SHL) {
     isSigned = false; /*sign irrelevant*/
-    if (VT == EVT::i16)
+    if (VT == MVT::i16)
       LC = RTLIB::SHL_I16;
-    else if (VT == EVT::i32)
+    else if (VT == MVT::i32)
       LC = RTLIB::SHL_I32;
-    else if (VT == EVT::i64)
+    else if (VT == MVT::i64)
       LC = RTLIB::SHL_I64;
-    else if (VT == EVT::i128)
+    else if (VT == MVT::i128)
       LC = RTLIB::SHL_I128;
   } else if (N->getOpcode() == ISD::SRL) {
     isSigned = false;
-    if (VT == EVT::i16)
+    if (VT == MVT::i16)
       LC = RTLIB::SRL_I16;
-    else if (VT == EVT::i32)
+    else if (VT == MVT::i32)
       LC = RTLIB::SRL_I32;
-    else if (VT == EVT::i64)
+    else if (VT == MVT::i64)
       LC = RTLIB::SRL_I64;
-    else if (VT == EVT::i128)
+    else if (VT == MVT::i128)
       LC = RTLIB::SRL_I128;
   } else {
     assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
     isSigned = true;
-    if (VT == EVT::i16)
+    if (VT == MVT::i16)
       LC = RTLIB::SRA_I16;
-    else if (VT == EVT::i32)
+    else if (VT == MVT::i32)
       LC = RTLIB::SRA_I32;
-    else if (VT == EVT::i64)
+    else if (VT == MVT::i64)
       LC = RTLIB::SRA_I64;
-    else if (VT == EVT::i128)
+    else if (VT == MVT::i128)
       LC = RTLIB::SRA_I128;
   }
 
@@ -1857,13 +1857,13 @@ void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
   DebugLoc dl = N->getDebugLoc();
 
   RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
-  if (VT == EVT::i16)
+  if (VT == MVT::i16)
     LC = RTLIB::SREM_I16;
-  else if (VT == EVT::i32)
+  else if (VT == MVT::i32)
     LC = RTLIB::SREM_I32;
-  else if (VT == EVT::i64)
+  else if (VT == MVT::i64)
     LC = RTLIB::SREM_I64;
-  else if (VT == EVT::i128)
+  else if (VT == MVT::i128)
     LC = RTLIB::SREM_I128;
   assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
 
@@ -1888,13 +1888,13 @@ void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
   DebugLoc dl = N->getDebugLoc();
 
   RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
-  if (VT == EVT::i16)
+  if (VT == MVT::i16)
     LC = RTLIB::UDIV_I16;
-  else if (VT == EVT::i32)
+  else if (VT == MVT::i32)
     LC = RTLIB::UDIV_I32;
-  else if (VT == EVT::i64)
+  else if (VT == MVT::i64)
     LC = RTLIB::UDIV_I64;
-  else if (VT == EVT::i128)
+  else if (VT == MVT::i128)
     LC = RTLIB::UDIV_I128;
   assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
 
@@ -1908,13 +1908,13 @@ void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
   DebugLoc dl = N->getDebugLoc();
 
   RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
-  if (VT == EVT::i16)
+  if (VT == MVT::i16)
     LC = RTLIB::UREM_I16;
-  else if (VT == EVT::i32)
+  else if (VT == MVT::i32)
     LC = RTLIB::UREM_I32;
-  else if (VT == EVT::i64)
+  else if (VT == MVT::i64)
     LC = RTLIB::UREM_I64;
-  else if (VT == EVT::i128)
+  else if (VT == MVT::i128)
     LC = RTLIB::UREM_I128;
   assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
 
@@ -2222,7 +2222,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
     Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
                            SVOffset+IncrementSize, NEVT,
                            isVolatile, MinAlign(Alignment, IncrementSize));
-    return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+    return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
   } else {
     // Big-endian - high bits are at low addresses.  Favor aligned stores at
     // the cost of some bit-fiddling.
@@ -2257,7 +2257,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
                            SVOffset+IncrementSize,
                            EVT::getIntegerVT(ExcessBits),
                            isVolatile, MinAlign(Alignment, IncrementSize));
-    return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+    return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
   }
 }
 
@@ -2288,11 +2288,11 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
     const uint64_t F32TwoE128 = 0x7F800000ULL;
 
     APInt FF(32, 0);
-    if (SrcVT == EVT::i32)
+    if (SrcVT == MVT::i32)
       FF = APInt(32, F32TwoE32);
-    else if (SrcVT == EVT::i64)
+    else if (SrcVT == MVT::i64)
       FF = APInt(32, F32TwoE64);
-    else if (SrcVT == EVT::i128)
+    else if (SrcVT == MVT::i128)
       FF = APInt(32, F32TwoE128);
     else
       assert(false && "Unsupported UINT_TO_FP!");
@@ -2323,7 +2323,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
     // Load the value out, extending it from f32 to the destination float type.
     // FIXME: Avoid the extend by constructing the right constant pool?
     SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
-                                   FudgePtr, NULL, 0, EVT::f32,
+                                   FudgePtr, NULL, 0, MVT::f32,
                                    false, Alignment);
     return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
   }
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 8801ceec90..195b9f258c 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -159,7 +159,7 @@ public:
   explicit DAGTypeLegalizer(SelectionDAG &dag)
     : TLI(dag.getTargetLoweringInfo()), DAG(dag),
     ValueTypeActions(TLI.getValueTypeActions()) {
-    assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE &&
+    assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
            "Too many value types for ValueTypeActions to hold!");
   }
 
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
index 8533866a07..0760c6326f 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
@@ -220,7 +220,7 @@ void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo,
 
   // Build a factor node to remember that this load is independent of the
   // other one.
-  Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
                       Hi.getValue(1));
 
   // Handle endianness of the load.
@@ -402,7 +402,7 @@ SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
                     SVOffset + IncrementSize,
                     isVolatile, MinAlign(Alignment, IncrementSize));
 
-  return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
 }
 
 
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index aa647fde1b..ca194305d9 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -306,7 +306,7 @@ SDValue VectorLegalizer::UnrollVectorOp(SDValue Op) {
         Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
                                   OperandEltVT,
                                   Operand,
-                                  DAG.getConstant(i, EVT::i32));
+                                  DAG.getConstant(i, MVT::i32));
       } else {
         // A scalar operand; just use it as is.
         Operands[j] = Operand;
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index a10d167579..1600b900d0 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -213,7 +213,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
   DebugLoc DL = N->getDebugLoc();
 
   // Turn it into a scalar SETCC.
-  return DAG.getNode(ISD::SETCC, DL, EVT::i1, LHS, RHS, N->getOperand(2));
+  return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
 }
 
 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
@@ -247,16 +247,16 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
     if (TLI.getBooleanContents() !=
         TargetLowering::ZeroOrNegativeOneBooleanContent)
       Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
-                        DAG.getValueType(EVT::i1));
+                        DAG.getValueType(MVT::i1));
     // Truncate to the final type.
     return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
   }
 
   // The SETCC result type is smaller than the vector element type.
-  // If the SetCC result is not sign-extended, chop it down to EVT::i1.
+  // If the SetCC result is not sign-extended, chop it down to MVT::i1.
   if (TLI.getBooleanContents() !=
         TargetLowering::ZeroOrNegativeOneBooleanContent)
-    Res = DAG.getNode(ISD::TRUNCATE, DL, EVT::i1, Res);
+    Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
   // Sign extend to the final type.
   return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
 }
@@ -725,7 +725,7 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
 
   // Build a factor node to remember that this load is independent of the
   // other one.
-  Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
+  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
                    Hi.getValue(1));
 
   // Legalized the chain result - switch anything that used the old chain to
@@ -1097,7 +1097,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
     Hi = DAG.getStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
                       isVol, MinAlign(Alignment, IncrementSize));
 
-  return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
+  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
 }
 
 
@@ -1660,7 +1660,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
  if (LdChain.size() == 1)
    NewChain = LdChain[0];
  else
-   NewChain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &LdChain[0],
+   NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LdChain[0],
                           LdChain.size());
 
   // Modified the chain - switch anything that used the old chain to use
@@ -1941,7 +1941,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
     return StChain[0];
   else
     return DAG.getNode(ISD::TokenFactor, dl,
-                       EVT::Other,&StChain[0],StChain.size());
+                       MVT::Other,&StChain[0],StChain.size());
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index ee83f068e1..fda1610b98 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -216,15 +216,15 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) {
   bool TryUnfold = false;
   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
     EVT VT = N->getValueType(i);
-    if (VT == EVT::Flag)
+    if (VT == MVT::Flag)
       return NULL;
-    else if (VT == EVT::Other)
+    else if (VT == MVT::Other)
       TryUnfold = true;
   }
   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
     const SDValue &Op = N->getOperand(i);
     EVT VT = Op.getNode()->getValueType(Op.getResNo());
-    if (VT == EVT::Flag)
+    if (VT == MVT::Flag)
       return NULL;
   }
 
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 5c7b8499e6..26da246c41 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -353,15 +353,15 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
   bool TryUnfold = false;
   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
     EVT VT = N->getValueType(i);
-    if (VT == EVT::Flag)
+    if (VT == MVT::Flag)
       return NULL;
-    else if (VT == EVT::Other)
+    else if (VT == MVT::Other)
       TryUnfold = true;
   }
   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
     const SDValue &Op = N->getOperand(i);
     EVT VT = Op.getNode()->getValueType(Op.getResNo());
-    if (VT == EVT::Flag)
+    if (VT == MVT::Flag)
       return NULL;
   }
 
@@ -630,7 +630,7 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
     if (Node->getOpcode() == ISD::INLINEASM) {
       // Inline asm can clobber physical defs.
       unsigned NumOps = Node->getNumOperands();
-      if (Node->getOperand(NumOps-1).getValueType() == EVT::Flag)
+      if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
         --NumOps;  // Ignore the flag operand.
 
       for (unsigned i = 2; i != NumOps;) {
@@ -1217,7 +1217,7 @@ static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU,
       return false;
     for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
       EVT VT = N->getValueType(i);
-      if (VT == EVT::Flag || VT == EVT::Other)
+      if (VT == MVT::Flag || VT == MVT::Other)
         continue;
       if (!N->hasAnyUseOfValue(i))
         continue;
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 4d2882a884..0b0aa269b6 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -111,7 +111,7 @@ void ScheduleDAGSDNodes::BuildSchedUnits() {
     // Scan up to find flagged preds.
     SDNode *N = NI;
     while (N->getNumOperands() &&
-           N->getOperand(N->getNumOperands()-1).getValueType() == EVT::Flag) {
+           N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
       N = N->getOperand(N->getNumOperands()-1).getNode();
       assert(N->getNodeId() == -1 && "Node already inserted!");
       N->setNodeId(NodeSUnit->NodeNum);
@@ -119,7 +119,7 @@ void ScheduleDAGSDNodes::BuildSchedUnits() {
     
     // Scan down to find any flagged succs.
     N = NI;
-    while (N->getValueType(N->getNumValues()-1) == EVT::Flag) {
+    while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
       SDValue FlagVal(N, N->getNumValues()-1);
       
       // There are either zero or one users of the Flag result.
@@ -190,8 +190,8 @@ void ScheduleDAGSDNodes::AddSchedEdges() {
         if (OpSU == SU) continue;           // In the same group.
 
         EVT OpVT = N->getOperand(i).getValueType();
-        assert(OpVT != EVT::Flag && "Flagged nodes should be in same sunit!");
-        bool isChain = OpVT == EVT::Other;
+        assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
+        bool isChain = OpVT == MVT::Other;
 
         unsigned PhysReg = 0;
         int Cost = 1;
@@ -244,9 +244,9 @@ void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
 /// not go into the resulting MachineInstr).
 unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) {
   unsigned N = Node->getNumValues();
-  while (N && Node->getValueType(N - 1) == EVT::Flag)
+  while (N && Node->getValueType(N - 1) == MVT::Flag)
     --N;
-  if (N && Node->getValueType(N - 1) == EVT::Other)
+  if (N && Node->getValueType(N - 1) == MVT::Other)
     --N;    // Skip over chain result.
   return N;
 }
@@ -266,9 +266,9 @@ unsigned ScheduleDAGSDNodes::CountOperands(SDNode *Node) {
 /// operand
 unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) {
   unsigned N = Node->getNumOperands();
-  while (N && Node->getOperand(N - 1).getValueType() == EVT::Flag)
+  while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
     --N;
-  if (N && Node->getOperand(N - 1).getValueType() == EVT::Other)
+  if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
     --N; // Ignore chain if it exists.
   return N;
 }
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
index d8736a12ad..12b5d143f8 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
@@ -70,7 +70,7 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
           if (Op.getNode() != Node || Op.getResNo() != ResNo)
             continue;
           EVT VT = Node->getValueType(Op.getResNo());
-          if (VT == EVT::Other || VT == EVT::Flag)
+          if (VT == MVT::Other || VT == MVT::Flag)
             continue;
           Match = false;
           if (User->isMachineOpcode()) {
@@ -238,8 +238,8 @@ ScheduleDAGSDNodes::AddRegisterOperand(MachineInstr *MI, SDValue Op,
                                        unsigned IIOpNum,
                                        const TargetInstrDesc *II,
                                        DenseMap<SDValue, unsigned> &VRBaseMap) {
-  assert(Op.getValueType() != EVT::Other &&
-         Op.getValueType() != EVT::Flag &&
+  assert(Op.getValueType() != MVT::Other &&
+         Op.getValueType() != MVT::Flag &&
          "Chain and flag operands should occur at end of operand list!");
   // Get/emit the operand.
   unsigned VReg = getVR(Op, VRBaseMap);
@@ -322,8 +322,8 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
     MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 0,
                                             ES->getTargetFlags()));
   } else {
-    assert(Op.getValueType() != EVT::Other &&
-           Op.getValueType() != EVT::Flag &&
+    assert(Op.getValueType() != MVT::Other &&
+           Op.getValueType() != MVT::Flag &&
            "Chain and flag operands should occur at end of operand list!");
     AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
   }
@@ -599,7 +599,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
   }
   case ISD::INLINEASM: {
     unsigned NumOps = Node->getNumOperands();
-    if (Node->getOperand(NumOps-1).getValueType() == EVT::Flag)
+    if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
       --NumOps;  // Ignore the flag operand.
       
     // Create the inline asm machine instruction.
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index afb5d94877..5b5558ab97 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -54,13 +54,13 @@ static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs) {
 }
 
 static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
-  switch (VT.getSimpleVT()) {
+  switch (VT.getSimpleVT().SimpleTy) {
   default: llvm_unreachable("Unknown FP format");
-  case EVT::f32:     return &APFloat::IEEEsingle;
-  case EVT::f64:     return &APFloat::IEEEdouble;
-  case EVT::f80:     return &APFloat::x87DoubleExtended;
-  case EVT::f128:    return &APFloat::IEEEquad;
-  case EVT::ppcf128: return &APFloat::PPCDoubleDouble;
+  case MVT::f32:     return &APFloat::IEEEsingle;
+  case MVT::f64:     return &APFloat::IEEEdouble;
+  case MVT::f80:     return &APFloat::x87DoubleExtended;
+  case MVT::f128:    return &APFloat::IEEEquad;
+  case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
   }
 }
 
@@ -83,7 +83,7 @@ bool ConstantFPSDNode::isValueValidForType(EVT VT,
   assert(VT.isFloatingPoint() && "Can only convert between FP types");
 
   // PPC long double cannot be converted to any other type.
-  if (VT == EVT::ppcf128 ||
+  if (VT == MVT::ppcf128 ||
       &Val.getSemantics() == &APFloat::PPCDoubleDouble)
     return false;
 
@@ -503,7 +503,7 @@ encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM,
 
 /// doNotCSE - Return true if CSE should not be performed for this node.
 static bool doNotCSE(SDNode *N) {
-  if (N->getValueType(0) == EVT::Flag)
+  if (N->getValueType(0) == MVT::Flag)
     return true; // Never CSE anything that produces a flag.
 
   switch (N->getOpcode()) {
@@ -518,7 +518,7 @@ static bool doNotCSE(SDNode *N) {
 
   // Check that remaining values produced are not flags.
   for (unsigned i = 1, e = N->getNumValues(); i != e; ++i)
-    if (N->getValueType(i) == EVT::Flag)
+    if (N->getValueType(i) == MVT::Flag)
       return true; // Never CSE anything that produces a flag.
 
   return false;
@@ -643,8 +643,8 @@ bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
     if (VT.isExtended()) {
       Erased = ExtendedValueTypeNodes.erase(VT);
     } else {
-      Erased = ValueTypeNodes[VT.getSimpleVT()] != 0;
-      ValueTypeNodes[VT.getSimpleVT()] = 0;
+      Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != 0;
+      ValueTypeNodes[VT.getSimpleVT().SimpleTy] = 0;
     }
     break;
   }
@@ -657,7 +657,7 @@ bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
   // Verify that the node was actually in one of the CSE maps, unless it has a
   // flag result (which cannot be CSE'd) or is one of the special cases that are
   // not subject to CSE.
-  if (!Erased && N->getValueType(N->getNumValues()-1) != EVT::Flag &&
+  if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag &&
       !N->isMachineOpcode() && !doNotCSE(N)) {
     N->dump(this);
     cerr << "\n";
@@ -788,7 +788,7 @@ void SelectionDAG::VerifyNode(SDNode *N) {
 /// given type.
 ///
 unsigned SelectionDAG::getEVTAlignment(EVT VT) const {
-  const Type *Ty = VT == EVT::iPTR ?
+  const Type *Ty = VT == MVT::iPTR ?
                    PointerType::get(Type::Int8Ty, 0) :
                    VT.getTypeForEVT();
 
@@ -799,7 +799,7 @@ unsigned SelectionDAG::getEVTAlignment(EVT VT) const {
 SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli)
   : TLI(tli), FLI(fli), DW(0),
     EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(),
-    getVTList(EVT::Other)), Root(getEntryNode()) {
+    getVTList(MVT::Other)), Root(getEntryNode()) {
   AllNodes.push_back(&EntryNode);
 }
 
@@ -950,7 +950,7 @@ SDValue SelectionDAG::getConstantFP(const ConstantFP& V, EVT VT, bool isTarget){
 SDValue SelectionDAG::getConstantFP(double Val, EVT VT, bool isTarget) {
   EVT EltVT =
     VT.isVector() ? VT.getVectorElementType() : VT;
-  if (EltVT==EVT::f32)
+  if (EltVT==MVT::f32)
     return getConstantFP(APFloat((float)Val), VT, isTarget);
   else
     return getConstantFP(APFloat(Val), VT, isTarget);
@@ -1084,7 +1084,7 @@ SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, EVT VT,
 
 SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) {
   FoldingSetNodeID ID;
-  AddNodeIDNode(ID, ISD::BasicBlock, getVTList(EVT::Other), 0, 0);
+  AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
   ID.AddPointer(MBB);
   void *IP = 0;
   if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
@@ -1097,11 +1097,12 @@ SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) {
 }
 
 SDValue SelectionDAG::getValueType(EVT VT) {
-  if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size())
-    ValueTypeNodes.resize(VT.getSimpleVT()+1);
+  if (VT.isSimple() && (unsigned)VT.getSimpleVT().SimpleTy >=
+      ValueTypeNodes.size())
+    ValueTypeNodes.resize(VT.getSimpleVT().SimpleTy+1);
 
   SDNode *&N = VT.isExtended() ?
-    ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()];
+    ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT().SimpleTy];
 
   if (N) return SDValue(N, 0);
   N = NodeAllocator.Allocate<VTSDNode>();
@@ -1299,7 +1300,7 @@ SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl,
                                unsigned LabelID) {
   FoldingSetNodeID ID;
   SDValue Ops[] = { Root };
-  AddNodeIDNode(ID, Opcode, getVTList(EVT::Other), &Ops[0], 1);
+  AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1);
   ID.AddInteger(LabelID);
   void *IP = 0;
   if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
@@ -1316,7 +1317,7 @@ SDValue SelectionDAG::getSrcValue(const Value *V) {
          "SrcValue is not a pointer?");
 
   FoldingSetNodeID ID;
-  AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(EVT::Other), 0, 0);
+  AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0);
   ID.AddPointer(V);
 
   void *IP = 0;
@@ -1338,7 +1339,7 @@ SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) {
 #endif
 
   FoldingSetNodeID ID;
-  AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(EVT::Other), 0, 0);
+  AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0);
   MO.Profile(ID);
 
   void *IP = 0;
@@ -1439,7 +1440,7 @@ SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1,
   if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
     if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) {
       // No compile time operations on this type yet.
-      if (N1C->getValueType(0) == EVT::ppcf128)
+      if (N1C->getValueType(0) == MVT::ppcf128)
         return SDValue();
 
       APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF());
@@ -2277,7 +2278,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
     case ISD::SINT_TO_FP: {
       const uint64_t zero[] = {0, 0};
       // No compile time operations on this type.
-      if (VT==EVT::ppcf128)
+      if (VT==MVT::ppcf128)
         break;
       APFloat apf = APFloat(APInt(BitWidth, 2, zero));
       (void)apf.convertFromAPInt(Val,
@@ -2286,9 +2287,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
       return getConstantFP(apf, VT);
     }
     case ISD::BIT_CONVERT:
-      if (VT == EVT::f32 && C->getValueType(0) == EVT::i32)
+      if (VT == MVT::f32 && C->getValueType(0) == MVT::i32)
         return getConstantFP(Val.bitsToFloat(), VT);
-      else if (VT == EVT::f64 && C->getValueType(0) == EVT::i64)
+      else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64)
         return getConstantFP(Val.bitsToDouble(), VT);
       break;
     case ISD::BSWAP:
@@ -2305,7 +2306,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
   // Constant fold unary operations with a floating point constant operand.
   if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) {
     APFloat V = C->getValueAPF();    // make copy
-    if (VT != EVT::ppcf128 && Operand.getValueType() != EVT::ppcf128) {
+    if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) {
       switch (Opcode) {
       case ISD::FNEG:
         V.changeSign();
@@ -2337,9 +2338,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
         return getConstant(api, VT);
       }
       case ISD::BIT_CONVERT:
-        if (VT == EVT::i32 && C->getValueType(0) == EVT::f32)
+        if (VT == MVT::i32 && C->getValueType(0) == MVT::f32)
           return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT);
-        else if (VT == EVT::i64 && C->getValueType(0) == EVT::f64)
+        else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64)
           return getConstant(V.bitcastToAPInt().getZExtValue(), VT);
         break;
       }
@@ -2450,7 +2451,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
 
   SDNode *N;
   SDVTList VTs = getVTList(VT);
-  if (VT != EVT::Flag) { // Don't CSE flag producing nodes
+  if (VT != MVT::Flag) { // Don't CSE flag producing nodes
     FoldingSetNodeID ID;
     SDValue Ops[1] = { Operand };
     AddNodeIDNode(ID, Opcode, VTs, Ops, 1);
@@ -2515,8 +2516,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
   switch (Opcode) {
   default: break;
   case ISD::TokenFactor:
-    assert(VT == EVT::Other && N1.getValueType() == EVT::Other &&
-           N2.getValueType() == EVT::Other && "Invalid token factor!");
+    assert(VT == MVT::Other && N1.getValueType() == MVT::Other &&
+           N2.getValueType() == MVT::Other && "Invalid token factor!");
     // Fold trivial token factors.
     if (N1.getOpcode() == ISD::EntryToken) return N2;
     if (N2.getOpcode() == ISD::EntryToken) return N1;
@@ -2606,7 +2607,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
     // Always fold shifts of i1 values so the code generator doesn't need to
     // handle them.  Since we know the size of the shift has to be less than the
     // size of the value, the shift/rotate count is guaranteed to be zero.
-    if (VT == EVT::i1)
+    if (VT == MVT::i1)
       return N1;
     break;
   case ISD::FP_ROUND_INREG: {
@@ -2747,7 +2748,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
       // Cannonicalize constant to RHS if commutative
       std::swap(N1CFP, N2CFP);
       std::swap(N1, N2);
-    } else if (N2CFP && VT != EVT::ppcf128) {
+    } else if (N2CFP && VT != MVT::ppcf128) {
       APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF();
       APFloat::opStatus s;
       switch (Opcode) {
@@ -2862,7 +2863,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
   // Memoize this node if possible.
   SDNode *N;
   SDVTList VTs = getVTList(VT);
-  if (VT != EVT::Flag) {
+  if (VT != MVT::Flag) {
     SDValue Ops[] = { N1, N2 };
     FoldingSetNodeID ID;
     AddNodeIDNode(ID, Opcode, VTs, Ops, 2);
@@ -2921,7 +2922,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
   case ISD::BRCOND:
     if (N2C) {
       if (N2C->getZExtValue()) // Unconditional branch
-        return getNode(ISD::BR, DL, EVT::Other, N1, N3);
+        return getNode(ISD::BR, DL, MVT::Other, N1, N3);
       else
         return N1;         // Never-taken branch
     }
@@ -2939,7 +2940,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
   // Memoize node if it doesn't produce a flag.
   SDNode *N;
   SDVTList VTs = getVTList(VT);
-  if (VT != EVT::Flag) {
+  if (VT != MVT::Flag) {
     SDValue Ops[] = { N1, N2, N3 };
     FoldingSetNodeID ID;
     AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
@@ -2993,7 +2994,7 @@ SDValue SelectionDAG::getStackArgumentTokenFactor(SDValue Chain) {
           ArgChains.push_back(SDValue(L, 1));
 
   // Build a tokenfactor for all the chains.
-  return getNode(ISD::TokenFactor, Chain.getDebugLoc(), EVT::Other,
+  return getNode(ISD::TokenFactor, Chain.getDebugLoc(), MVT::Other,
                  &ArgChains[0], ArgChains.size());
 }
 
@@ -3041,7 +3042,7 @@ static SDValue getMemsetStringVal(EVT VT, DebugLoc dl, SelectionDAG &DAG,
     if (VT.isInteger())
       return DAG.getConstant(0, VT);
     unsigned NumElts = VT.getVectorNumElements();
-    EVT EltVT = (VT.getVectorElementType() == EVT::f32) ? EVT::i32 : EVT::i64;
+    EVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
     return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
                        DAG.getConstant(0, EVT::getVectorVT(EltVT, NumElts)));
   }
@@ -3105,7 +3106,7 @@ bool MeetsMaxMemopRequirement(std::vector<EVT> &MemOps,
   bool isSrcConst = isa<ConstantSDNode>(Src);
   bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses();
   EVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG);
-  if (VT != EVT::iAny) {
+  if (VT != MVT::iAny) {
     unsigned NewAlign = (unsigned)
       TLI.getTargetData()->getABITypeAlignment(VT.getTypeForEVT());
     // If source is a string constant, this will require an unaligned load.
@@ -3113,14 +3114,14 @@ bool MeetsMaxMemopRequirement(std::vector<EVT> &MemOps,
       if (Dst.getOpcode() != ISD::FrameIndex) {
         // Can't change destination alignment. It requires a unaligned store.
         if (AllowUnalign)
-          VT = EVT::iAny;
+          VT = MVT::iAny;
       } else {
         int FI = cast<FrameIndexSDNode>(Dst)->getIndex();
         MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
         if (MFI->isFixedObjectIndex(FI)) {
           // Can't change destination alignment. It requires a unaligned store.
           if (AllowUnalign)
-            VT = EVT::iAny;
+            VT = MVT::iAny;
         } else {
           // Give the stack frame object a larger alignment if needed.
           if (MFI->getObjectAlignment(FI) < NewAlign)
@@ -3131,21 +3132,21 @@ bool MeetsMaxMemopRequirement(std::vector<EVT> &MemOps,
     }
   }
 
-  if (VT == EVT::iAny) {
+  if (VT == MVT::iAny) {
     if (AllowUnalign) {
-      VT = EVT::i64;
+      VT = MVT::i64;
     } else {
       switch (Align & 7) {
-      case 0:  VT = EVT::i64; break;
-      case 4:  VT = EVT::i32; break;
-      case 2:  VT = EVT::i16; break;
-      default: VT = EVT::i8;  break;
+      case 0:  VT = MVT::i64; break;
+      case 4:  VT = MVT::i32; break;
+      case 2:  VT = MVT::i16; break;
+      default: VT = MVT::i8;  break;
       }
     }
 
-    EVT LVT = EVT::i64;
+    EVT LVT = MVT::i64;
     while (!TLI.isTypeLegal(LVT))
-      LVT = (EVT::SimpleValueType)(LVT.getSimpleVT() - 1);
+      LVT = (MVT::SimpleValueType)(LVT.getSimpleVT().SimpleTy - 1);
     assert(LVT.isInteger());
 
     if (VT.bitsGT(LVT))
@@ -3158,14 +3159,14 @@ bool MeetsMaxMemopRequirement(std::vector<EVT> &MemOps,
     while (VTSize > Size) {
       // For now, only use non-vector load / store's for the left-over pieces.
       if (VT.isVector()) {
-        VT = EVT::i64;
+        VT = MVT::i64;
         while (!TLI.isTypeLegal(VT))
-          VT = (EVT::SimpleValueType)(VT.getSimpleVT() - 1);
+          VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1);
         VTSize = VT.getSizeInBits() / 8;
       } else {
         // This can result in a type that is not legal on the target, e.g.
         // 1 or 2 bytes on PPC.
-        VT = (EVT::SimpleValueType)(VT.getSimpleVT() - 1);
+        VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1);
         VTSize >>= 1;
       }
     }
@@ -3240,7 +3241,7 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl,
     DstOff += VTSize;
   }
 
-  return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
                      &OutChains[0], OutChains.size());
 }
 
@@ -3283,7 +3284,7 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl,
     LoadChains.push_back(Value.getValue(1));
     SrcOff += VTSize;
   }
-  Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
                       &LoadChains[0], LoadChains.size());
   OutChains.clear();
   for (unsigned i = 0; i < NumMemOps; i++) {
@@ -3298,7 +3299,7 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl,
     DstOff += VTSize;
   }
 
-  return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
                      &OutChains[0], OutChains.size());
 }
 
@@ -3333,7 +3334,7 @@ static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl,
     DstOff += VTSize;
   }
 
-  return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
+  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
                      &OutChains[0], OutChains.size());
 }
 
@@ -3478,10 +3479,10 @@ SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst,
   Entry.Node = Dst; Entry.Ty = IntPtrTy;
   Args.push_back(Entry);
   // Extend or truncate the argument to be an i32 value for the call.
-  if (Src.getValueType().bitsGT(EVT::i32))
-    Src = getNode(ISD::TRUNCATE, dl, EVT::i32, Src);
+  if (Src.getValueType().bitsGT(MVT::i32))
+    Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
   else
-    Src = getNode(ISD::ZERO_EXTEND, dl, EVT::i32, Src);
+    Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
   Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
   Args.push_back(Entry);
   Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false;
@@ -3510,7 +3511,7 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
   if (Alignment == 0)  // Ensure that codegen never sees alignment 0
     Alignment = getEVTAlignment(MemVT);
 
-  SDVTList VTs = getVTList(VT, EVT::Other);
+  SDVTList VTs = getVTList(VT, MVT::Other);
   FoldingSetNodeID ID;
   ID.AddInteger(MemVT.getRawBits());
   SDValue Ops[] = {Chain, Ptr, Cmp, Swp};
@@ -3549,7 +3550,7 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
   if (Alignment == 0)  // Ensure that codegen never sees alignment 0
     Alignment = getEVTAlignment(MemVT);
 
-  SDVTList VTs = getVTList(VT, EVT::Other);
+  SDVTList VTs = getVTList(VT, MVT::Other);
   FoldingSetNodeID ID;
   ID.AddInteger(MemVT.getRawBits());
   SDValue Ops[] = {Chain, Ptr, Val};
@@ -3600,7 +3601,7 @@ SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
                                   bool ReadMem, bool WriteMem) {
   // Memoize the node unless it returns a flag.
   MemIntrinsicSDNode *N;
-  if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) {
+  if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
     FoldingSetNodeID ID;
     AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
     void *IP = 0;
@@ -3652,7 +3653,7 @@ SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
          "Unindexed load with an offset!");
 
   SDVTList VTs = Indexed ?
-    getVTList(VT, Ptr.getValueType(), EVT::Other) : getVTList(VT, EVT::Other);
+    getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other);
   SDValue Ops[] = { Chain, Ptr, Offset };
   FoldingSetNodeID ID;
   AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
@@ -3708,7 +3709,7 @@ SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val,
   if (Alignment == 0)  // Ensure that codegen never sees alignment 0
     Alignment = getEVTAlignment(VT);
 
-  SDVTList VTs = getVTList(EVT::Other);
+  SDVTList VTs = getVTList(MVT::Other);
   SDValue Undef = getUNDEF(Ptr.getValueType());
   SDValue Ops[] = { Chain, Val, Ptr, Undef };
   FoldingSetNodeID ID;
@@ -3743,7 +3744,7 @@ SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
   if (Alignment == 0)  // Ensure that codegen never sees alignment 0
     Alignment = getEVTAlignment(VT);
 
-  SDVTList VTs = getVTList(EVT::Other);
+  SDVTList VTs = getVTList(MVT::Other);
   SDValue Undef = getUNDEF(Ptr.getValueType());
   SDValue Ops[] = { Chain, Val, Ptr, Undef };
   FoldingSetNodeID ID;
@@ -3768,7 +3769,7 @@ SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base,
   StoreSDNode *ST = cast<StoreSDNode>(OrigStore);
   assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
          "Store is already a indexed store!");
-  SDVTList VTs = getVTList(Base.getValueType(), EVT::Other);
+  SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
   SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
   FoldingSetNodeID ID;
   AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
@@ -3791,7 +3792,7 @@ SDValue SelectionDAG::getVAArg(EVT VT, DebugLoc dl,
                                SDValue Chain, SDValue Ptr,
                                SDValue SV) {
   SDValue Ops[] = { Chain, Ptr, SV };
-  return getNode(ISD::VAARG, dl, getVTList(VT, EVT::Other), Ops, 3);
+  return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3);
 }
 
 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
@@ -3844,7 +3845,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
   SDNode *N;
   SDVTList VTs = getVTList(VT);
 
-  if (VT != EVT::Flag) {
+  if (VT != MVT::Flag) {
     FoldingSetNodeID ID;
     AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps);
     void *IP = 0;
@@ -3896,7 +3897,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
   case ISD::SRL_PARTS:
   case ISD::SHL_PARTS:
     if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
-        cast<VTSDNode>(N3.getOperand(1))->getVT() != EVT::i1)
+        cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
       return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0));
     else if (N3.getOpcode() == ISD::AND)
       if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
@@ -3912,7 +3913,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
 
   // Memoize the node unless it returns a flag.
   SDNode *N;
-  if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) {
+  if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
     FoldingSetNodeID ID;
     AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
     void *IP = 0;
@@ -4407,7 +4408,7 @@ SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
                                   unsigned NumOps) {
   // If an identical node already exists, use it.
   void *IP = 0;
-  if (VTs.VTs[VTs.NumVTs-1] != EVT::Flag) {
+  if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) {
     FoldingSetNodeID ID;
     AddNodeIDNode(ID, Opc, VTs, Ops, NumOps);
     if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP))
@@ -4581,7 +4582,7 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
 /// else return NULL.
 SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
                                       const SDValue *Ops, unsigned NumOps) {
-  if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) {
+  if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
     FoldingSetNodeID ID;
     AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
     void *IP = 0;
@@ -4996,7 +4997,7 @@ void SDNode::Profile(FoldingSetNodeID &ID) const {
 }
 
 static ManagedStatic<std::set<EVT, EVT::compareRawBits> > EVTs;
-static EVT VTs[EVT::LAST_VALUETYPE];
+static EVT VTs[MVT::LAST_VALUETYPE];
 static ManagedStatic<sys::SmartMutex<true> > VTMutex;
 
 /// getValueTypeList - Return a pointer to the specified value type.
@@ -5006,8 +5007,8 @@ const EVT *SDNode::getValueTypeList(EVT VT) {
   if (VT.isExtended()) {
     return &(*EVTs->insert(VT).first);
   } else {
-    VTs[VT.getSimpleVT()] = VT;
-    return &VTs[VT.getSimpleVT()];
+    VTs[VT.getSimpleVT().SimpleTy] = VT;
+    return &VTs[VT.getSimpleVT().SimpleTy];
   }
 }
 
@@ -5449,7 +5450,7 @@ void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const {
 
   for (unsigned i = 0, e = getNumValues(); i != e; ++i) {
     if (i) OS << ",";
-    if (getValueType(i) == EVT::Other)
+    if (getValueType(i) == MVT::Other)
       OS << "ch";
     else
       OS << getValueType(i).getEVTString();
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index 1d02bffb61..4662fb06ef 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -496,11 +496,11 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
                         ValueVT, &Ops[0], NumIntermediates);
     } else if (PartVT.isFloatingPoint()) {
       // FP split into multiple FP parts (for ppcf128)
-      assert(ValueVT == EVT(EVT::ppcf128) && PartVT == EVT(EVT::f64) &&
+      assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
              "Unexpected split");
       SDValue Lo, Hi;
-      Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(EVT::f64), Parts[0]);
-      Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(EVT::f64), Parts[1]);
+      Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]);
+      Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]);
       if (TLI.isBigEndian())
         std::swap(Lo, Hi);
       Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
@@ -774,7 +774,7 @@ SDValue SelectionDAGLowering::getRoot() {
   }
 
   // Otherwise, we have to make a token factor node.
-  SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
+  SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
                                &PendingLoads[0], PendingLoads.size());
   PendingLoads.clear();
   DAG.setRoot(Root);
@@ -804,7 +804,7 @@ SDValue SelectionDAGLowering::getControlRoot() {
       PendingExports.push_back(Root);
   }
 
-  Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
+  Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
                      &PendingExports[0],
                      PendingExports.size());
   PendingExports.clear();
@@ -961,7 +961,7 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
       // conventions. The frontend should mark functions whose return values
       // require promoting with signext or zeroext attributes.
       if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
-        EVT MinVT = TLI.getRegisterType(EVT::i32);
+        EVT MinVT = TLI.getRegisterType(MVT::i32);
         if (VT.bitsLT(MinVT))
           VT = MinVT;
       }
@@ -995,7 +995,7 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
                           Outs, getCurDebugLoc(), DAG);
 
   // Verify that the target's LowerReturn behaved as expected.
-  assert(Chain.getNode() && Chain.getValueType() == EVT::Other &&
+  assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
          "LowerReturn didn't return a valid chain!");
 
   // Update the DAG with the new chain value resulting from return lowering.
@@ -1250,7 +1250,7 @@ void SelectionDAGLowering::visitBr(BranchInst &I) {
     // If this is not a fall-through branch, emit the branch.
     if (Succ0MBB != NextBlock)
       DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
-                              EVT::Other, getControlRoot(),
+                              MVT::Other, getControlRoot(),
                               DAG.getBasicBlock(Succ0MBB)));
     return;
   }
@@ -1334,7 +1334,7 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
       SDValue True = DAG.getConstant(1, CondLHS.getValueType());
       Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
     } else
-      Cond = DAG.getSetCC(dl, EVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
+      Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
   } else {
     assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
 
@@ -1345,12 +1345,12 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
     EVT VT = CmpOp.getValueType();
 
     if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
-      Cond = DAG.getSetCC(dl, EVT::i1, CmpOp, DAG.getConstant(High, VT),
+      Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
                           ISD::SETLE);
     } else {
       SDValue SUB = DAG.getNode(ISD::SUB, dl,
                                 VT, CmpOp, DAG.getConstant(Low, VT));
-      Cond = DAG.getSetCC(dl, EVT::i1, SUB,
+      Cond = DAG.getSetCC(dl, MVT::i1, SUB,
                           DAG.getConstant(High-Low, VT), ISD::SETULE);
     }
   }
@@ -1374,7 +1374,7 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
     Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
   }
   SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
-                               EVT::Other, getControlRoot(), Cond,
+                               MVT::Other, getControlRoot(), Cond,
                                DAG.getBasicBlock(CB.TrueBB));
 
   // If the branch was constant folded, fix up the CFG.
@@ -1389,7 +1389,7 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
     if (CB.FalseBB == NextBlock)
       DAG.setRoot(BrCond);
     else
-      DAG.setRoot(DAG.getNode(ISD::BR, dl, EVT::Other, BrCond,
+      DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
                               DAG.getBasicBlock(CB.FalseBB)));
   }
 }
@@ -1403,7 +1403,7 @@ void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
                                      JT.Reg, PTy);
   SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
   DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
-                          EVT::Other, Index.getValue(1),
+                          MVT::Other, Index.getValue(1),
                           Table, Index));
 }
 
@@ -1452,13 +1452,13 @@ void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
     NextBlock = BBI;
 
   SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
-                               EVT::Other, CopyTo, CMP,
+                               MVT::Other, CopyTo, CMP,
                                DAG.getBasicBlock(JT.Default));
 
   if (JT.MBB == NextBlock)
     DAG.setRoot(BrCond);
   else
-    DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, BrCond,
+    DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
                             DAG.getBasicBlock(JT.MBB)));
 }
 
@@ -1502,13 +1502,13 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
   CurMBB->addSuccessor(MBB);
 
   SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
-                                EVT::Other, CopyTo, RangeCmp,
+                                MVT::Other, CopyTo, RangeCmp,
                                 DAG.getBasicBlock(B.Default));
 
   if (MBB == NextBlock)
     DAG.setRoot(BrRange);
   else
-    DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, CopyTo,
+    DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
                             DAG.getBasicBlock(MBB)));
 }
 
@@ -1537,7 +1537,7 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
   CurMBB->addSuccessor(NextMBB);
 
   SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
-                              EVT::Other, getControlRoot(),
+                              MVT::Other, getControlRoot(),
                               AndCmp, DAG.getBasicBlock(B.TargetBB));
 
   // Set NextBlock to be the MBB immediately after the current one, if any.
@@ -1550,7 +1550,7 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
   if (NextMBB == NextBlock)
     DAG.setRoot(BrAnd);
   else
-    DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, BrAnd,
+    DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
                             DAG.getBasicBlock(NextMBB)));
 }
 
@@ -1575,7 +1575,7 @@ void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
 
   // Drop into normal successor.
   DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
-                          EVT::Other, getControlRoot(),
+                          MVT::Other, getControlRoot(),
                           DAG.getBasicBlock(Return)));
 }
 
@@ -1669,8 +1669,8 @@ bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
 
 static inline bool areJTsAllowed(const TargetLowering &TLI) {
   return !DisableJumpTables &&
-          (TLI.isOperationLegalOrCustom(ISD::BR_JT, EVT::Other) ||
-           TLI.isOperationLegalOrCustom(ISD::BRIND, EVT::Other));
+          (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
+           TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
 }
 
 static APInt ComputeRange(const APInt &First, const APInt &Last) {
@@ -2096,7 +2096,7 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
     CurMBB->addSuccessor(Default);
     if (Default != NextBlock)
       DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
-                              EVT::Other, getControlRoot(),
+                              MVT::Other, getControlRoot(),
                               DAG.getBasicBlock(Default)));
     return;
   }
@@ -2680,7 +2680,7 @@ void SelectionDAGLowering::visitGetElementPtr(User &I) {
         if (PtrBits < 64) {
           OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
                                 TLI.getPointerTy(),
-                                DAG.getConstant(Offs, EVT::i64));
+                                DAG.getConstant(Offs, MVT::i64));
         } else
           OffsVal = DAG.getIntPtrConstant(Offs);
         N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
@@ -2770,7 +2770,7 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
                           DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
 
   SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
-  SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), EVT::Other);
+  SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
   SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
                             VTs, Ops, 3);
   setValue(&I, DSA);
@@ -2826,7 +2826,7 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) {
 
   if (!ConstantMemory) {
     SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
-                                  EVT::Other,
+                                  MVT::Other,
                                   &Chains[0], NumValues);
     if (isVolatile)
       DAG.setRoot(Chain);
@@ -2872,7 +2872,7 @@ void SelectionDAGLowering::visitStore(StoreInst &I) {
                              isVolatile, Alignment);
 
   DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
-                          EVT::Other, &Chains[0], NumValues));
+                          MVT::Other, &Chains[0], NumValues));
 }
 
 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
@@ -2918,7 +2918,7 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
   }
 #endif // NDEBUG
   if (HasChain)
-    ValueVTs.push_back(EVT::Other);
+    ValueVTs.push_back(MVT::Other);
 
   SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
 
@@ -3033,11 +3033,11 @@ void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
 /// where Op is the hexidecimal representation of floating point value.
 static SDValue
 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
-  SDValue t1 = DAG.getNode(ISD::AND, dl, EVT::i32, Op,
-                           DAG.getConstant(0x007fffff, EVT::i32));
-  SDValue t2 = DAG.getNode(ISD::OR, dl, EVT::i32, t1,
-                           DAG.getConstant(0x3f800000, EVT::i32));
-  return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t2);
+  SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
+                           DAG.getConstant(0x007fffff, MVT::i32));
+  SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
+                           DAG.getConstant(0x3f800000, MVT::i32));
+  return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
 }
 
 /// GetExponent - Get the exponent:
@@ -3048,19 +3048,19 @@ GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
 static SDValue
 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
             DebugLoc dl) {
-  SDValue t0 = DAG.getNode(ISD::AND, dl, EVT::i32, Op,
-                           DAG.getConstant(0x7f800000, EVT::i32));
-  SDValue t1 = DAG.getNode(ISD::SRL, dl, EVT::i32, t0,
+  SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
+                           DAG.getConstant(0x7f800000, MVT::i32));
+  SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
                            DAG.getConstant(23, TLI.getPointerTy()));
-  SDValue t2 = DAG.getNode(ISD::SUB, dl, EVT::i32, t1,
-                           DAG.getConstant(127, EVT::i32));
-  return DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, t2);
+  SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
+                           DAG.getConstant(127, MVT::i32));
+  return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
 }
 
 /// getF32Constant - Get 32-bit floating point constant.
 static SDValue
 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
-  return DAG.getConstantFP(APFloat(APInt(32, Flt)), EVT::f32);
+  return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
 }
 
 /// Inlined utility function to implement binary input atomic intrinsics for
@@ -3087,7 +3087,7 @@ SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
   SDValue Op1 = getValue(I.getOperand(1));
   SDValue Op2 = getValue(I.getOperand(2));
 
-  SDVTList VTs = DAG.getVTList(Op1.getValueType(), EVT::i1);
+  SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
   SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
 
   setValue(&I, Result);
@@ -3101,7 +3101,7 @@ SelectionDAGLowering::visitExp(CallInst &I) {
   SDValue result;
   DebugLoc dl = getCurDebugLoc();
 
-  if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
+  if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
     SDValue Op = getValue(I.getOperand(1));
 
@@ -3110,16 +3110,16 @@ SelectionDAGLowering::visitExp(CallInst &I) {
     //
     //   #define LOG2OFe 1.4426950f
     //   IntegerPartOfX = ((int32_t)(X * LOG2OFe));
-    SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, Op,
+    SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
                              getF32Constant(DAG, 0x3fb8aa3b));
-    SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, t0);
+    SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
 
     //   FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
-    SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
-    SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, t1);
+    SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
+    SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
 
     //   IntegerPartOfX <<= 23;
-    IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
+    IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
                                  DAG.getConstant(23, TLI.getPointerTy()));
 
     if (LimitFloatPrecision <= 6) {
@@ -3130,20 +3130,20 @@ SelectionDAGLowering::visitExp(CallInst &I) {
       //       (0.735607626f + 0.252464424f * x) * x;
       //
       // error 0.0144103317, which is 6 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3e814304));
-      SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3f3c50c8));
-      SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3f7f5e7e));
-      SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,EVT::i32, t5);
+      SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
 
       // Add the exponent into the result in integer domain.
-      SDValue t6 = DAG.getNode(ISD::ADD, dl, EVT::i32,
+      SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
                                TwoToFracPartOfX, IntegerPartOfX);
 
-      result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t6);
+      result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
     } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
       // For floating-point precision of 12:
       //
@@ -3153,23 +3153,23 @@ SelectionDAGLowering::visitExp(CallInst &I) {
       //         (0.224338339f + 0.792043434e-1f * x) * x) * x;
       //
       // 0.000107046256 error, which is 13 to 14 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3da235e3));
-      SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3e65b8f3));
-      SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3f324b07));
-      SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x3f7ff8fd));
-      SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,EVT::i32, t7);
+      SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
 
       // Add the exponent into the result in integer domain.
-      SDValue t8 = DAG.getNode(ISD::ADD, dl, EVT::i32,
+      SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
                                TwoToFracPartOfX, IntegerPartOfX);
 
-      result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t8);
+      result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
     } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
       // For floating-point precision of 18:
       //
@@ -3182,33 +3182,33 @@ SelectionDAGLowering::visitExp(CallInst &I) {
       //               (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
       //
       // error 2.47208000*10^(-7), which is better than 18 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3924b03e));
-      SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3ab24b87));
-      SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3c1d8c17));
-      SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x3d634a1d));
-      SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
-      SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
+      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+      SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
                                getF32Constant(DAG, 0x3e75fe14));
-      SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
-      SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
+      SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+      SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
                                 getF32Constant(DAG, 0x3f317234));
-      SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
-      SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
+      SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
+      SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
                                 getF32Constant(DAG, 0x3f800000));
       SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
-                                             EVT::i32, t13);
+                                             MVT::i32, t13);
 
       // Add the exponent into the result in integer domain.
-      SDValue t14 = DAG.getNode(ISD::ADD, dl, EVT::i32,
+      SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
                                 TwoToFracPartOfX, IntegerPartOfX);
 
-      result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t14);
+      result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
     }
   } else {
     // No special expansion.
@@ -3227,14 +3227,14 @@ SelectionDAGLowering::visitLog(CallInst &I) {
   SDValue result;
   DebugLoc dl = getCurDebugLoc();
 
-  if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
+  if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
     SDValue Op = getValue(I.getOperand(1));
-    SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
+    SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
 
     // Scale the exponent by log(2) [0.69314718f].
     SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
-    SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, EVT::f32, Exp,
+    SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
                                         getF32Constant(DAG, 0x3f317218));
 
     // Get the significand and build it into a floating-point number with
@@ -3249,16 +3249,16 @@ SelectionDAGLowering::visitLog(CallInst &I) {
       //       (1.4034025f - 0.23903021f * x) * x;
       //
       // error 0.0034276066, which is better than 8 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0xbe74c456));
-      SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x3fb3a2b1));
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
-      SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
                                           getF32Constant(DAG, 0x3f949a29));
 
       result = DAG.getNode(ISD::FADD, dl,
-                           EVT::f32, LogOfExponent, LogOfMantissa);
+                           MVT::f32, LogOfExponent, LogOfMantissa);
     } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
       // For floating-point precision of 12:
       //
@@ -3269,22 +3269,22 @@ SelectionDAGLowering::visitLog(CallInst &I) {
       //           (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
       //
       // error 0.000061011436, which is 14 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0xbd67b6d6));
-      SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x3ee4f4b8));
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
-      SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3fbc278b));
-      SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x40348e95));
-      SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
-      SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
                                           getF32Constant(DAG, 0x3fdef31a));
 
       result = DAG.getNode(ISD::FADD, dl,
-                           EVT::f32, LogOfExponent, LogOfMantissa);
+                           MVT::f32, LogOfExponent, LogOfMantissa);
     } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
       // For floating-point precision of 18:
       //
@@ -3297,28 +3297,28 @@ SelectionDAGLowering::visitLog(CallInst &I) {
       //               (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
       //
       // error 0.0000023660568, which is better than 18 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0xbc91e5ac));
-      SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x3e4350aa));
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
-      SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3f60d3e3));
-      SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x4011cdf0));
-      SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x406cfd1c));
-      SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
-      SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
+      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+      SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
                                getF32Constant(DAG, 0x408797cb));
-      SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
-      SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t10,
+      SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+      SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
                                           getF32Constant(DAG, 0x4006dcab));
 
       result = DAG.getNode(ISD::FADD, dl,
-                           EVT::f32, LogOfExponent, LogOfMantissa);
+                           MVT::f32, LogOfExponent, LogOfMantissa);
     }
   } else {
     // No special expansion.
@@ -3337,10 +3337,10 @@ SelectionDAGLowering::visitLog2(CallInst &I) {
   SDValue result;
   DebugLoc dl = getCurDebugLoc();
 
-  if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
+  if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
     SDValue Op = getValue(I.getOperand(1));
-    SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
+    SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
 
     // Get the exponent.
     SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
@@ -3357,16 +3357,16 @@ SelectionDAGLowering::visitLog2(CallInst &I) {
       //   Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
       //
       // error 0.0049451742, which is more than 7 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0xbeb08fe0));
-      SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x40019463));
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
-      SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
                                            getF32Constant(DAG, 0x3fd6633d));
 
       result = DAG.getNode(ISD::FADD, dl,
-                           EVT::f32, LogOfExponent, Log2ofMantissa);
+                           MVT::f32, LogOfExponent, Log2ofMantissa);
     } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
       // For floating-point precision of 12:
       //
@@ -3377,22 +3377,22 @@ SelectionDAGLowering::visitLog2(CallInst &I) {
       //           (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
       //
       // error 0.0000876136000, which is better than 13 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0xbda7262e));
-      SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x3f25280b));
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
-      SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x4007b923));
-      SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x40823e2f));
-      SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
-      SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
                                            getF32Constant(DAG, 0x4020d29c));
 
       result = DAG.getNode(ISD::FADD, dl,
-                           EVT::f32, LogOfExponent, Log2ofMantissa);
+                           MVT::f32, LogOfExponent, Log2ofMantissa);
     } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
       // For floating-point precision of 18:
       //
@@ -3406,28 +3406,28 @@ SelectionDAGLowering::visitLog2(CallInst &I) {
       //                 0.25691327e-1f * x) * x) * x) * x) * x) * x;
       //
       // error 0.0000018516, which is better than 18 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0xbcd2769e));
-      SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x3e8ce0b9));
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
-      SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3fa22ae7));
-      SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x40525723));
-      SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x40aaf200));
-      SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
-      SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
+      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+      SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
                                getF32Constant(DAG, 0x40c39dad));
-      SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
-      SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t10,
+      SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+      SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
                                            getF32Constant(DAG, 0x4042902c));
 
       result = DAG.getNode(ISD::FADD, dl,
-                           EVT::f32, LogOfExponent, Log2ofMantissa);
+                           MVT::f32, LogOfExponent, Log2ofMantissa);
     }
   } else {
     // No special expansion.
@@ -3446,14 +3446,14 @@ SelectionDAGLowering::visitLog10(CallInst &I) {
   SDValue result;
   DebugLoc dl = getCurDebugLoc();
 
-  if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
+  if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
     SDValue Op = getValue(I.getOperand(1));
-    SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
+    SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
 
     // Scale the exponent by log10(2) [0.30102999f].
     SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
-    SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, EVT::f32, Exp,
+    SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
                                         getF32Constant(DAG, 0x3e9a209a));
 
     // Get the significand and build it into a floating-point number with
@@ -3468,16 +3468,16 @@ SelectionDAGLowering::visitLog10(CallInst &I) {
       //       (0.60948995f - 0.10380950f * x) * x;
       //
       // error 0.0014886165, which is 6 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0xbdd49a13));
-      SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x3f1c0789));
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
-      SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
                                             getF32Constant(DAG, 0x3f011300));
 
       result = DAG.getNode(ISD::FADD, dl,
-                           EVT::f32, LogOfExponent, Log10ofMantissa);
+                           MVT::f32, LogOfExponent, Log10ofMantissa);
     } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
       // For floating-point precision of 12:
       //
@@ -3487,19 +3487,19 @@ SelectionDAGLowering::visitLog10(CallInst &I) {
       //         (-0.31664806f + 0.47637168e-1f * x) * x) * x;
       //
       // error 0.00019228036, which is better than 12 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3d431f31));
-      SDValue t1 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x3ea21fb2));
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
-      SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3f6ae232));
-      SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
-      SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
                                             getF32Constant(DAG, 0x3f25f7c3));
 
       result = DAG.getNode(ISD::FADD, dl,
-                           EVT::f32, LogOfExponent, Log10ofMantissa);
+                           MVT::f32, LogOfExponent, Log10ofMantissa);
     } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
       // For floating-point precision of 18:
       //
@@ -3511,25 +3511,25 @@ SelectionDAGLowering::visitLog10(CallInst &I) {
       //             (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
       //
       // error 0.0000037995730, which is better than 18 bits
-      SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3c5d51ce));
-      SDValue t1 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0,
+      SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
                                getF32Constant(DAG, 0x3e00685a));
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
-      SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3efb6798));
-      SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3f88d192));
-      SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x3fc4316c));
-      SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
-      SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t8,
+      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+      SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
                                             getF32Constant(DAG, 0x3f57ce70));
 
       result = DAG.getNode(ISD::FADD, dl,
-                           EVT::f32, LogOfExponent, Log10ofMantissa);
+                           MVT::f32, LogOfExponent, Log10ofMantissa);
     }
   } else {
     // No special expansion.
@@ -3548,18 +3548,18 @@ SelectionDAGLowering::visitExp2(CallInst &I) {
   SDValue result;
   DebugLoc dl = getCurDebugLoc();
 
-  if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
+  if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
     SDValue Op = getValue(I.getOperand(1));
 
-    SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, Op);
+    SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
 
     //   FractionalPartOfX = x - (float)IntegerPartOfX;
-    SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
-    SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, Op, t1);
+    SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
+    SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
 
     //   IntegerPartOfX <<= 23;
-    IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
+    IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
                                  DAG.getConstant(23, TLI.getPointerTy()));
 
     if (LimitFloatPrecision <= 6) {
@@ -3570,19 +3570,19 @@ SelectionDAGLowering::visitExp2(CallInst &I) {
       //       (0.735607626f + 0.252464424f * x) * x;
       //
       // error 0.0144103317, which is 6 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3e814304));
-      SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3f3c50c8));
-      SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3f7f5e7e));
-      SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t5);
+      SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
       SDValue TwoToFractionalPartOfX =
-        DAG.getNode(ISD::ADD, dl, EVT::i32, t6, IntegerPartOfX);
+        DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
 
       result = DAG.getNode(ISD::BIT_CONVERT, dl,
-                           EVT::f32, TwoToFractionalPartOfX);
+                           MVT::f32, TwoToFractionalPartOfX);
     } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
       // For floating-point precision of 12:
       //
@@ -3592,22 +3592,22 @@ SelectionDAGLowering::visitExp2(CallInst &I) {
       //         (0.224338339f + 0.792043434e-1f * x) * x) * x;
       //
       // error 0.000107046256, which is 13 to 14 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3da235e3));
-      SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3e65b8f3));
-      SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3f324b07));
-      SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x3f7ff8fd));
-      SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t7);
+      SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
       SDValue TwoToFractionalPartOfX =
-        DAG.getNode(ISD::ADD, dl, EVT::i32, t8, IntegerPartOfX);
+        DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
 
       result = DAG.getNode(ISD::BIT_CONVERT, dl,
-                           EVT::f32, TwoToFractionalPartOfX);
+                           MVT::f32, TwoToFractionalPartOfX);
     } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
       // For floating-point precision of 18:
       //
@@ -3619,31 +3619,31 @@ SelectionDAGLowering::visitExp2(CallInst &I) {
       //             (0.961591928e-2f +
       //               (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
       // error 2.47208000*10^(-7), which is better than 18 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3924b03e));
-      SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3ab24b87));
-      SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3c1d8c17));
-      SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x3d634a1d));
-      SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
-      SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
+      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+      SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
                                getF32Constant(DAG, 0x3e75fe14));
-      SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
-      SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
+      SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+      SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
                                 getF32Constant(DAG, 0x3f317234));
-      SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
-      SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
+      SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
+      SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
                                 getF32Constant(DAG, 0x3f800000));
-      SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t13);
+      SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
       SDValue TwoToFractionalPartOfX =
-        DAG.getNode(ISD::ADD, dl, EVT::i32, t14, IntegerPartOfX);
+        DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
 
       result = DAG.getNode(ISD::BIT_CONVERT, dl,
-                           EVT::f32, TwoToFractionalPartOfX);
+                           MVT::f32, TwoToFractionalPartOfX);
     }
   } else {
     // No special expansion.
@@ -3664,8 +3664,8 @@ SelectionDAGLowering::visitPow(CallInst &I) {
   DebugLoc dl = getCurDebugLoc();
   bool IsExp10 = false;
 
-  if (getValue(Val).getValueType() == EVT::f32 &&
-      getValue(I.getOperand(2)).getValueType() == EVT::f32 &&
+  if (getValue(Val).getValueType() == MVT::f32 &&
+      getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
       LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
     if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
       if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
@@ -3683,16 +3683,16 @@ SelectionDAGLowering::visitPow(CallInst &I) {
     //
     //   #define LOG2OF10 3.3219281f
     //   IntegerPartOfX = (int32_t)(x * LOG2OF10);
-    SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, Op,
+    SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
                              getF32Constant(DAG, 0x40549a78));
-    SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, t0);
+    SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
 
     //   FractionalPartOfX = x - (float)IntegerPartOfX;
-    SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
-    SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, t1);
+    SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
+    SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
 
     //   IntegerPartOfX <<= 23;
-    IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
+    IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
                                  DAG.getConstant(23, TLI.getPointerTy()));
 
     if (LimitFloatPrecision <= 6) {
@@ -3703,19 +3703,19 @@ SelectionDAGLowering::visitPow(CallInst &I) {
       //       (0.735607626f + 0.252464424f * x) * x;
       //
       // error 0.0144103317, which is 6 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3e814304));
-      SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3f3c50c8));
-      SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3f7f5e7e));
-      SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t5);
+      SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
       SDValue TwoToFractionalPartOfX =
-        DAG.getNode(ISD::ADD, dl, EVT::i32, t6, IntegerPartOfX);
+        DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
 
       result = DAG.getNode(ISD::BIT_CONVERT, dl,
-                           EVT::f32, TwoToFractionalPartOfX);
+                           MVT::f32, TwoToFractionalPartOfX);
     } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
       // For floating-point precision of 12:
       //
@@ -3725,22 +3725,22 @@ SelectionDAGLowering::visitPow(CallInst &I) {
       //         (0.224338339f + 0.792043434e-1f * x) * x) * x;
       //
       // error 0.000107046256, which is 13 to 14 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3da235e3));
-      SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3e65b8f3));
-      SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3f324b07));
-      SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x3f7ff8fd));
-      SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t7);
+      SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
       SDValue TwoToFractionalPartOfX =
-        DAG.getNode(ISD::ADD, dl, EVT::i32, t8, IntegerPartOfX);
+        DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
 
       result = DAG.getNode(ISD::BIT_CONVERT, dl,
-                           EVT::f32, TwoToFractionalPartOfX);
+                           MVT::f32, TwoToFractionalPartOfX);
     } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
       // For floating-point precision of 18:
       //
@@ -3752,31 +3752,31 @@ SelectionDAGLowering::visitPow(CallInst &I) {
       //             (0.961591928e-2f +
       //               (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
       // error 2.47208000*10^(-7), which is better than 18 bits
-      SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
+      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
                                getF32Constant(DAG, 0x3924b03e));
-      SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
+      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
                                getF32Constant(DAG, 0x3ab24b87));
-      SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
-      SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
+      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
+      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
                                getF32Constant(DAG, 0x3c1d8c17));
-      SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
-      SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
+      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
+      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
                                getF32Constant(DAG, 0x3d634a1d));
-      SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
-      SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
+      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
+      SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
                                getF32Constant(DAG, 0x3e75fe14));
-      SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
-      SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
+      SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
+      SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
                                 getF32Constant(DAG, 0x3f317234));
-      SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
-      SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
+      SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
+      SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
                                 getF32Constant(DAG, 0x3f800000));
-      SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t13);
+      SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
       SDValue TwoToFractionalPartOfX =
-        DAG.getNode(ISD::ADD, dl, EVT::i32, t14, IntegerPartOfX);
+        DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
 
       result = DAG.getNode(ISD::BIT_CONVERT, dl,
-                           EVT::f32, TwoToFractionalPartOfX);
+                           MVT::f32, TwoToFractionalPartOfX);
     }
   } else {
     // No special expansion.
@@ -3973,14 +3973,14 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
       return 0;
 
     Value *Variable = DI.getVariable();
-    DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, EVT::Other, getRoot(),
+    DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
                             getValue(DI.getAddress()), getValue(Variable)));
     return 0;
   }
   case Intrinsic::eh_exception: {
     // Insert the EXCEPTIONADDR instruction.
     assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
-    SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), EVT::Other);
+    SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
     SDValue Ops[1];
     Ops[0] = DAG.getRoot();
     SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
@@ -3993,7 +3993,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
   case Intrinsic::eh_selector_i64: {
     MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
     EVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
-                         EVT::i32 : EVT::i64);
+                         MVT::i32 : MVT::i64);
 
     if (MMI) {
       if (CurMBB->isLandingPad())
@@ -4008,7 +4008,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
       }
 
       // Insert the EHSELECTION instruction.
-      SDVTList VTs = DAG.getVTList(VT, EVT::Other);
+      SDVTList VTs = DAG.getVTList(VT, MVT::Other);
       SDValue Ops[2];
       Ops[0] = getValue(I.getOperand(1));
       Ops[1] = getRoot();
@@ -4026,7 +4026,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
   case Intrinsic::eh_typeid_for_i64: {
     MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
     EVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
-                         EVT::i32 : EVT::i64);
+                         MVT::i32 : MVT::i64);
 
     if (MMI) {
       // Find the type id for the given typeinfo.
@@ -4047,7 +4047,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
       MMI->setCallsEHReturn(true);
       DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
-                              EVT::Other,
+                              MVT::Other,
                               getControlRoot(),
                               getValue(I.getOperand(1)),
                               getValue(I.getOperand(2))));
@@ -4165,13 +4165,13 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     return 0;
   case Intrinsic::pcmarker: {
     SDValue Tmp = getValue(I.getOperand(1));
-    DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, EVT::Other, getRoot(), Tmp));
+    DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
     return 0;
   }
   case Intrinsic::readcyclecounter: {
     SDValue Op = getRoot();
     SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
-                              DAG.getVTList(EVT::i64, EVT::Other),
+                              DAG.getVTList(MVT::i64, MVT::Other),
                               &Op, 1);
     setValue(&I, Tmp);
     DAG.setRoot(Tmp.getValue(1));
@@ -4206,14 +4206,14 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
   case Intrinsic::stacksave: {
     SDValue Op = getRoot();
     SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
-              DAG.getVTList(TLI.getPointerTy(), EVT::Other), &Op, 1);
+              DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
     setValue(&I, Tmp);
     DAG.setRoot(Tmp.getValue(1));
     return 0;
   }
   case Intrinsic::stackrestore: {
     SDValue Tmp = getValue(I.getOperand(1));
-    DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, EVT::Other, getRoot(), Tmp));
+    DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
     return 0;
   }
   case Intrinsic::stackprotector: {
@@ -4254,7 +4254,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     Ops[5] = DAG.getSrcValue(F);
 
     SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
-                              DAG.getVTList(TLI.getPointerTy(), EVT::Other),
+                              DAG.getVTList(TLI.getPointerTy(), MVT::Other),
                               Ops, 6);
 
     setValue(&I, Tmp);
@@ -4278,12 +4278,12 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     return 0;
 
   case Intrinsic::flt_rounds: {
-    setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, EVT::i32));
+    setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
     return 0;
   }
 
   case Intrinsic::trap: {
-    DAG.setRoot(DAG.getNode(ISD::TRAP, dl,EVT::Other, getRoot()));
+    DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
     return 0;
   }
 
@@ -4306,7 +4306,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     Ops[1] = getValue(I.getOperand(1));
     Ops[2] = getValue(I.getOperand(2));
     Ops[3] = getValue(I.getOperand(3));
-    DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, EVT::Other, &Ops[0], 4));
+    DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
     return 0;
   }
 
@@ -4316,7 +4316,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     for (int x = 1; x < 6; ++x)
       Ops[x] = getValue(I.getOperand(x));
 
-    DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, EVT::Other, &Ops[0], 6));
+    DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
     return 0;
   }
   case Intrinsic::atomic_cmp_swap: {
@@ -4639,25 +4639,25 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
           // FIXME: We capture more information than the dag can represent.  For
           // now, just use the tightest assertzext/assertsext possible.
           bool isSExt = true;
-          EVT FromVT(EVT::Other);
+          EVT FromVT(MVT::Other);
           if (NumSignBits == RegSize)
-            isSExt = true, FromVT = EVT::i1;   // ASSERT SEXT 1
+            isSExt = true, FromVT = MVT::i1;   // ASSERT SEXT 1
           else if (NumZeroBits >= RegSize-1)
-            isSExt = false, FromVT = EVT::i1;  // ASSERT ZEXT 1
+            isSExt = false, FromVT = MVT::i1;  // ASSERT ZEXT 1
           else if (NumSignBits > RegSize-8)
-            isSExt = true, FromVT = EVT::i8;   // ASSERT SEXT 8
+            isSExt = true, FromVT = MVT::i8;   // ASSERT SEXT 8
           else if (NumZeroBits >= RegSize-8)
-            isSExt = false, FromVT = EVT::i8;  // ASSERT ZEXT 8
+            isSExt = false, FromVT = MVT::i8;  // ASSERT ZEXT 8
           else if (NumSignBits > RegSize-16)
-            isSExt = true, FromVT = EVT::i16;  // ASSERT SEXT 16
+            isSExt = true, FromVT = MVT::i16;  // ASSERT SEXT 16
           else if (NumZeroBits >= RegSize-16)
-            isSExt = false, FromVT = EVT::i16; // ASSERT ZEXT 16
+            isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
           else if (NumSignBits > RegSize-32)
-            isSExt = true, FromVT = EVT::i32;  // ASSERT SEXT 32
+            isSExt = true, FromVT = MVT::i32;  // ASSERT SEXT 32
           else if (NumZeroBits >= RegSize-32)
-            isSExt = false, FromVT = EVT::i32; // ASSERT ZEXT 32
+            isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
 
-          if (FromVT != EVT::Other) {
+          if (FromVT != MVT::Other) {
             P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
                             RegisterVT, P, DAG.getValueType(FromVT));
 
@@ -4724,7 +4724,7 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
     //        = op c3, ..., f2
     Chain = Chains[NumRegs-1];
   else
-    Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Chains[0], NumRegs);
+    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
 }
 
 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
@@ -4757,11 +4757,11 @@ static const TargetRegisterClass *
 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
                       const TargetLowering &TLI,
                       const TargetRegisterInfo *TRI) {
-  EVT FoundVT = EVT::Other;
+  EVT FoundVT = MVT::Other;
   const TargetRegisterClass *FoundRC = 0;
   for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
        E = TRI->regclass_end(); RCI != E; ++RCI) {
-    EVT ThisVT = EVT::Other;
+    EVT ThisVT = MVT::Other;
 
     const TargetRegisterClass *RC = *RCI;
     // If none of the the value types for this register class are valid, we
@@ -4772,14 +4772,14 @@ isAllocatableRegister(unsigned Reg, MachineFunction &MF,
         // If we have already found this register in a different register class,
         // choose the one with the largest VT specified.  For example, on
         // PowerPC, we favor f64 register classes over f32.
-        if (FoundVT == EVT::Other || FoundVT.bitsLT(*I)) {
+        if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
           ThisVT = *I;
           break;
         }
       }
     }
 
-    if (ThisVT == EVT::Other) continue;
+    if (ThisVT == MVT::Other) continue;
 
     // NOTE: This isn't ideal.  In particular, this might allocate the
     // frame pointer in functions that need it (due to them not being taken
@@ -4836,10 +4836,10 @@ public:
 
   /// getCallOperandValEVT - Return the EVT of the Value* that this operand
   /// corresponds to.  If there is no Value* for this operand, it returns
-  /// EVT::Other.
+  /// MVT::Other.
   EVT getCallOperandValEVT(const TargetLowering &TLI,
                            const TargetData *TD) const {
-    if (CallOperandVal == 0) return EVT::Other;
+    if (CallOperandVal == 0) return MVT::Other;
 
     if (isa<BasicBlock>(CallOperandVal))
       return TLI.getPointerTy();
@@ -4932,7 +4932,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
                                      OpInfo.ConstraintVT);
 
   unsigned NumRegs = 1;
-  if (OpInfo.ConstraintVT != EVT::Other) {
+  if (OpInfo.ConstraintVT != MVT::Other) {
     // If this is a FP input in an integer register (or visa versa) insert a bit
     // cast of the input value.  More generally, handle any case where the input
     // value disagrees with the register class we plan to stick this in.
@@ -4968,7 +4968,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
   // assign it now.
   if (unsigned AssignedReg = PhysReg.first) {
     const TargetRegisterClass *RC = PhysReg.second;
-    if (OpInfo.ConstraintVT == EVT::Other)
+    if (OpInfo.ConstraintVT == MVT::Other)
       ValueVT = *RC->vt_begin();
 
     // Get the actual register value type.  This is important, because the user
@@ -5002,7 +5002,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
   // for this reference.
   if (const TargetRegisterClass *RC = PhysReg.second) {
     RegVT = *RC->vt_begin();
-    if (OpInfo.ConstraintVT == EVT::Other)
+    if (OpInfo.ConstraintVT == MVT::Other)
       ValueVT = RegVT;
 
     // Create the appropriate number of virtual registers.
@@ -5116,7 +5116,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
     ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
     SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
 
-    EVT OpVT = EVT::Other;
+    EVT OpVT = MVT::Other;
 
     // Compute the value type for each operand.
     switch (OpInfo.Type) {
@@ -5252,7 +5252,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
   std::vector<SDValue> AsmNodeOperands;
   AsmNodeOperands.push_back(SDValue());  // reserve space for input chain
   AsmNodeOperands.push_back(
-          DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), EVT::Other));
+          DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
 
 
   // Loop over all of the inputs, copying the operand values into the
@@ -5440,7 +5440,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
   if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
 
   Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
-                      DAG.getVTList(EVT::Other, EVT::Flag),
+                      DAG.getVTList(MVT::Other, MVT::Flag),
                       &AsmNodeOperands[0], AsmNodeOperands.size());
   Flag = Chain.getValue(1);
 
@@ -5501,7 +5501,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
                                     getValue(StoresToEmit[i].second),
                                     StoresToEmit[i].second, 0));
   if (!OutChains.empty())
-    Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
+    Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
                         &OutChains[0], OutChains.size());
   DAG.setRoot(Chain);
 }
@@ -5518,7 +5518,7 @@ void SelectionDAGLowering::visitMalloc(MallocInst &I) {
   uint64_t ElementSize = TD->getTypeAllocSize(I.getType()->getElementType());
   if (ElementSize != 1) {
     // Src is always 32-bits, make sure the constant fits.
-    assert(Src.getValueType() == EVT::i32);
+    assert(Src.getValueType() == MVT::i32);
     ElementSize = (uint32_t)ElementSize;
     Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
                       Src, DAG.getConstant(ElementSize, Src.getValueType()));
@@ -5572,7 +5572,7 @@ void SelectionDAGLowering::visitFree(FreeInst &I) {
 
 void SelectionDAGLowering::visitVAStart(CallInst &I) {
   DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
-                          EVT::Other, getRoot(),
+                          MVT::Other, getRoot(),
                           getValue(I.getOperand(1)),
                           DAG.getSrcValue(I.getOperand(1))));
 }
@@ -5587,14 +5587,14 @@ void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
 
 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
   DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
-                          EVT::Other, getRoot(),
+                          MVT::Other, getRoot(),
                           getValue(I.getOperand(1)),
                           DAG.getSrcValue(I.getOperand(1))));
 }
 
 void SelectionDAGLowering::visitVACopy(CallInst &I) {
   DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
-                          EVT::Other, getRoot(),
+                          MVT::Other, getRoot(),
                           getValue(I.getOperand(1)),
                           getValue(I.getOperand(2)),
                           DAG.getSrcValue(I.getOperand(1)),
@@ -5715,7 +5715,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
                     Outs, Ins, dl, DAG, InVals);
 
   // Verify that the target's LowerCall behaved as expected.
-  assert(Chain.getNode() && Chain.getValueType() == EVT::Other &&
+  assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
          "LowerCall didn't return a valid chain!");
   assert((!isTailCall || InVals.empty()) &&
          "LowerCall emitted a return value for a tail call!");
@@ -5871,7 +5871,7 @@ LowerArguments(BasicBlock *LLVMBB) {
                                              dl, DAG, InVals);
 
   // Verify that the target's LowerFormalArguments behaved as expected.
-  assert(NewRoot.getNode() && NewRoot.getValueType() == EVT::Other &&
+  assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
          "LowerFormalArguments didn't return a valid chain!");
   assert(InVals.size() == Ins.size() &&
          "LowerFormalArguments didn't emit the correct number of values!");
@@ -6039,9 +6039,9 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
       // use CreateRegForValue to create registers, so it always creates
       // exactly one register for each non-void instruction.
       EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
-      if (VT == EVT::Other || !TLI.isTypeLegal(VT)) {
-        // Promote EVT::i1.
-        if (VT == EVT::i1)
+      if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
+        // Promote MVT::i1.
+        if (VT == MVT::i1)
           VT = TLI.getTypeToTransformTo(VT);
         else {
           SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 97bb3b3ef9..3d1327f13e 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -421,7 +421,7 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo() {
     
     // Otherwise, add all chain operands to the worklist.
     for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-      if (N->getOperand(i).getValueType() == EVT::Other)
+      if (N->getOperand(i).getValueType() == MVT::Other)
         Worklist.push_back(N->getOperand(i).getNode());
     
     // If this is a CopyToReg with a vreg dest, process it.
@@ -1098,7 +1098,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
   Ops.push_back(InOps[1]);  // input asm string.
 
   unsigned i = 2, e = InOps.size();
-  if (InOps[e-1].getValueType() == EVT::Flag)
+  if (InOps[e-1].getValueType() == MVT::Flag)
     --e;  // Don't process a flag operand if it is here.
   
   while (i != e) {
@@ -1236,7 +1236,7 @@ bool SelectionDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
   // a cycle in the scheduling graph.
 
   EVT VT = Root->getValueType(Root->getNumValues()-1);
-  while (VT == EVT::Flag) {
+  while (VT == MVT::Flag) {
     SDNode *FU = findFlagUse(Root);
     if (FU == NULL)
       break;
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index ef45110361..3b1100bb41 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -85,9 +85,9 @@ namespace llvm {
     static std::string getEdgeAttributes(const void *Node, EdgeIter EI) {
       SDValue Op = EI.getNode()->getOperand(EI.getOperand());
       EVT VT = Op.getValueType();
-      if (VT == EVT::Flag)
+      if (VT == MVT::Flag)
         return "color=red,style=bold";
-      else if (VT == EVT::Other)
+      else if (VT == MVT::Other)
         return "color=blue,style=dashed";
       return "";
     }
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index c7ddf0adb9..958851f082 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -250,8 +250,8 @@ static void InitLibcallNames(const char **Names) {
 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
 /// UNKNOWN_LIBCALL if there is none.
 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
-  if (OpVT == EVT::f32) {
-    if (RetVT == EVT::f64)
+  if (OpVT == MVT::f32) {
+    if (RetVT == MVT::f64)
       return FPEXT_F32_F64;
   }
   return UNKNOWN_LIBCALL;
@@ -260,17 +260,17 @@ RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
 /// UNKNOWN_LIBCALL if there is none.
 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
-  if (RetVT == EVT::f32) {
-    if (OpVT == EVT::f64)
+  if (RetVT == MVT::f32) {
+    if (OpVT == MVT::f64)
       return FPROUND_F64_F32;
-    if (OpVT == EVT::f80)
+    if (OpVT == MVT::f80)
       return FPROUND_F80_F32;
-    if (OpVT == EVT::ppcf128)
+    if (OpVT == MVT::ppcf128)
       return FPROUND_PPCF128_F32;
-  } else if (RetVT == EVT::f64) {
-    if (OpVT == EVT::f80)
+  } else if (RetVT == MVT::f64) {
+    if (OpVT == MVT::f80)
       return FPROUND_F80_F64;
-    if (OpVT == EVT::ppcf128)
+    if (OpVT == MVT::ppcf128)
       return FPROUND_PPCF128_F64;
   }
   return UNKNOWN_LIBCALL;
@@ -279,37 +279,37 @@ RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
 /// UNKNOWN_LIBCALL if there is none.
 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
-  if (OpVT == EVT::f32) {
-    if (RetVT == EVT::i8)
+  if (OpVT == MVT::f32) {
+    if (RetVT == MVT::i8)
       return FPTOSINT_F32_I8;
-    if (RetVT == EVT::i16)
+    if (RetVT == MVT::i16)
       return FPTOSINT_F32_I16;
-    if (RetVT == EVT::i32)
+    if (RetVT == MVT::i32)
       return FPTOSINT_F32_I32;
-    if (RetVT == EVT::i64)
+    if (RetVT == MVT::i64)
       return FPTOSINT_F32_I64;
-    if (RetVT == EVT::i128)
+    if (RetVT == MVT::i128)
       return FPTOSINT_F32_I128;
-  } else if (OpVT == EVT::f64) {
-    if (RetVT == EVT::i32)
+  } else if (OpVT == MVT::f64) {
+    if (RetVT == MVT::i32)
       return FPTOSINT_F64_I32;
-    if (RetVT == EVT::i64)
+    if (RetVT == MVT::i64)
       return FPTOSINT_F64_I64;
-    if (RetVT == EVT::i128)
+    if (RetVT == MVT::i128)
       return FPTOSINT_F64_I128;
-  } else if (OpVT == EVT::f80) {
-    if (RetVT == EVT::i32)
+  } else if (OpVT == MVT::f80) {
+    if (RetVT == MVT::i32)
       return FPTOSINT_F80_I32;
-    if (RetVT == EVT::i64)
+    if (RetVT == MVT::i64)
       return FPTOSINT_F80_I64;
-    if (RetVT == EVT::i128)
+    if (RetVT == MVT::i128)
       return FPTOSINT_F80_I128;
-  } else if (OpVT == EVT::ppcf128) {
-    if (RetVT == EVT::i32)
+  } else if (OpVT == MVT::ppcf128) {
+    if (RetVT == MVT::i32)
       return FPTOSINT_PPCF128_I32;
-    if (RetVT == EVT::i64)
+    if (RetVT == MVT::i64)
       return FPTOSINT_PPCF128_I64;
-    if (RetVT == EVT::i128)
+    if (RetVT == MVT::i128)
       return FPTOSINT_PPCF128_I128;
   }
   return UNKNOWN_LIBCALL;
@@ -318,37 +318,37 @@ RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
 /// UNKNOWN_LIBCALL if there is none.
 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
-  if (OpVT == EVT::f32) {
-    if (RetVT == EVT::i8)
+  if (OpVT == MVT::f32) {
+    if (RetVT == MVT::i8)
       return FPTOUINT_F32_I8;
-    if (RetVT == EVT::i16)
+    if (RetVT == MVT::i16)
       return FPTOUINT_F32_I16;
-    if (RetVT == EVT::i32)
+    if (RetVT == MVT::i32)
       return FPTOUINT_F32_I32;
-    if (RetVT == EVT::i64)
+    if (RetVT == MVT::i64)
       return FPTOUINT_F32_I64;
-    if (RetVT == EVT::i128)
+    if (RetVT == MVT::i128)
       return FPTOUINT_F32_I128;
-  } else if (OpVT == EVT::f64) {
-    if (RetVT == EVT::i32)
+  } else if (OpVT == MVT::f64) {
+    if (RetVT == MVT::i32)
       return FPTOUINT_F64_I32;
-    if (RetVT == EVT::i64)
+    if (RetVT == MVT::i64)
       return FPTOUINT_F64_I64;
-    if (RetVT == EVT::i128)
+    if (RetVT == MVT::i128)
       return FPTOUINT_F64_I128;
-  } else if (OpVT == EVT::f80) {
-    if (RetVT == EVT::i32)
+  } else if (OpVT == MVT::f80) {
+    if (RetVT == MVT::i32)
       return FPTOUINT_F80_I32;
-    if (RetVT == EVT::i64)
+    if (RetVT == MVT::i64)
       return FPTOUINT_F80_I64;
-    if (RetVT == EVT::i128)
+    if (RetVT == MVT::i128)
       return FPTOUINT_F80_I128;
-  } else if (OpVT == EVT::ppcf128) {
-    if (RetVT == EVT::i32)
+  } else if (OpVT == MVT::ppcf128) {
+    if (RetVT == MVT::i32)
       return FPTOUINT_PPCF128_I32;
-    if (RetVT == EVT::i64)
+    if (RetVT == MVT::i64)
       return FPTOUINT_PPCF128_I64;
-    if (RetVT == EVT::i128)
+    if (RetVT == MVT::i128)
       return FPTOUINT_PPCF128_I128;
   }
   return UNKNOWN_LIBCALL;
@@ -357,32 +357,32 @@ RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
 /// UNKNOWN_LIBCALL if there is none.
 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
-  if (OpVT == EVT::i32) {
-    if (RetVT == EVT::f32)
+  if (OpVT == MVT::i32) {
+    if (RetVT == MVT::f32)
       return SINTTOFP_I32_F32;
-    else if (RetVT == EVT::f64)
+    else if (RetVT == MVT::f64)
       return SINTTOFP_I32_F64;
-    else if (RetVT == EVT::f80)
+    else if (RetVT == MVT::f80)
       return SINTTOFP_I32_F80;
-    else if (RetVT == EVT::ppcf128)
+    else if (RetVT == MVT::ppcf128)
       return SINTTOFP_I32_PPCF128;
-  } else if (OpVT == EVT::i64) {
-    if (RetVT == EVT::f32)
+  } else if (OpVT == MVT::i64) {
+    if (RetVT == MVT::f32)
       return SINTTOFP_I64_F32;
-    else if (RetVT == EVT::f64)
+    else if (RetVT == MVT::f64)
       return SINTTOFP_I64_F64;
-    else if (RetVT == EVT::f80)
+    else if (RetVT == MVT::f80)
       return SINTTOFP_I64_F80;
-    else if (RetVT == EVT::ppcf128)
+    else if (RetVT == MVT::ppcf128)
       return SINTTOFP_I64_PPCF128;
-  } else if (OpVT == EVT::i128) {
-    if (RetVT == EVT::f32)
+  } else if (OpVT == MVT::i128) {
+    if (RetVT == MVT::f32)
       return SINTTOFP_I128_F32;
-    else if (RetVT == EVT::f64)
+    else if (RetVT == MVT::f64)
       return SINTTOFP_I128_F64;
-    else if (RetVT == EVT::f80)
+    else if (RetVT == MVT::f80)
       return SINTTOFP_I128_F80;
-    else if (RetVT == EVT::ppcf128)
+    else if (RetVT == MVT::ppcf128)
       return SINTTOFP_I128_PPCF128;
   }
   return UNKNOWN_LIBCALL;
@@ -391,32 +391,32 @@ RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
 /// UNKNOWN_LIBCALL if there is none.
 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
-  if (OpVT == EVT::i32) {
-    if (RetVT == EVT::f32)
+  if (OpVT == MVT::i32) {
+    if (RetVT == MVT::f32)
       return UINTTOFP_I32_F32;
-    else if (RetVT == EVT::f64)
+    else if (RetVT == MVT::f64)
       return UINTTOFP_I32_F64;
-    else if (RetVT == EVT::f80)
+    else if (RetVT == MVT::f80)
       return UINTTOFP_I32_F80;
-    else if (RetVT == EVT::ppcf128)
+    else if (RetVT == MVT::ppcf128)
       return UINTTOFP_I32_PPCF128;
-  } else if (OpVT == EVT::i64) {
-    if (RetVT == EVT::f32)
+  } else if (OpVT == MVT::i64) {
+    if (RetVT == MVT::f32)
       return UINTTOFP_I64_F32;
-    else if (RetVT == EVT::f64)
+    else if (RetVT == MVT::f64)
       return UINTTOFP_I64_F64;
-    else if (RetVT == EVT::f80)
+    else if (RetVT == MVT::f80)
       return UINTTOFP_I64_F80;
-    else if (RetVT == EVT::ppcf128)
+    else if (RetVT == MVT::ppcf128)
       return UINTTOFP_I64_PPCF128;
-  } else if (OpVT == EVT::i128) {
-    if (RetVT == EVT::f32)
+  } else if (OpVT == MVT::i128) {
+    if (RetVT == MVT::f32)
       return UINTTOFP_I128_F32;
-    else if (RetVT == EVT::f64)
+    else if (RetVT == MVT::f64)
       return UINTTOFP_I128_F64;
-    else if (RetVT == EVT::f80)
+    else if (RetVT == MVT::f80)
       return UINTTOFP_I128_F80;
-    else if (RetVT == EVT::ppcf128)
+    else if (RetVT == MVT::ppcf128)
       return UINTTOFP_I128_PPCF128;
   }
   return UNKNOWN_LIBCALL;
@@ -456,48 +456,49 @@ TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof)
   memset(CondCodeActions, 0, sizeof(CondCodeActions));
 
   // Set default actions for various operations.
-  for (unsigned VT = 0; VT != (unsigned)EVT::LAST_VALUETYPE; ++VT) {
+  for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
     // Default all indexed load / store to expand.
     for (unsigned IM = (unsigned)ISD::PRE_INC;
          IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
-      setIndexedLoadAction(IM, (EVT::SimpleValueType)VT, Expand);
-      setIndexedStoreAction(IM, (EVT::SimpleValueType)VT, Expand);
+      setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
+      setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
     }
     
     // These operations default to expand.
-    setOperationAction(ISD::FGETSIGN, (EVT::SimpleValueType)VT, Expand);
-    setOperationAction(ISD::CONCAT_VECTORS, (EVT::SimpleValueType)VT, Expand);
+    setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
+    setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
   }
 
   // Most targets ignore the @llvm.prefetch intrinsic.
-  setOperationAction(ISD::PREFETCH, EVT::Other, Expand);
+  setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
   
   // ConstantFP nodes default to expand.  Targets can either change this to 
   // Legal, in which case all fp constants are legal, or use addLegalFPImmediate
   // to optimize expansions for certain constants.
-  setOperationAction(ISD::ConstantFP, EVT::f32, Expand);
-  setOperationAction(ISD::ConstantFP, EVT::f64, Expand);
-  setOperationAction(ISD::ConstantFP, EVT::f80, Expand);
+  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
+  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
+  setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
 
   // These library functions default to expand.
-  setOperationAction(ISD::FLOG , EVT::f64, Expand);
-  setOperationAction(ISD::FLOG2, EVT::f64, Expand);
-  setOperationAction(ISD::FLOG10,EVT::f64, Expand);
-  setOperationAction(ISD::FEXP , EVT::f64, Expand);
-  setOperationAction(ISD::FEXP2, EVT::f64, Expand);
-  setOperationAction(ISD::FLOG , EVT::f32, Expand);
-  setOperationAction(ISD::FLOG2, EVT::f32, Expand);
-  setOperationAction(ISD::FLOG10,EVT::f32, Expand);
-  setOperationAction(ISD::FEXP , EVT::f32, Expand);
-  setOperationAction(ISD::FEXP2, EVT::f32, Expand);
+  setOperationAction(ISD::FLOG , MVT::f64, Expand);
+  setOperationAction(ISD::FLOG2, MVT::f64, Expand);
+  setOperationAction(ISD::FLOG10,MVT::f64, Expand);
+  setOperationAction(ISD::FEXP , MVT::f64, Expand);
+  setOperationAction(ISD::FEXP2, MVT::f64, Expand);
+  setOperationAction(ISD::FLOG , MVT::f32, Expand);
+  setOperationAction(ISD::FLOG2, MVT::f32, Expand);
+  setOperationAction(ISD::FLOG10,MVT::f32, Expand);
+  setOperationAction(ISD::FEXP , MVT::f32, Expand);
+  setOperationAction(ISD::FEXP2, MVT::f32, Expand);
 
   // Default ISD::TRAP to expand (which turns it into abort).
-  setOperationAction(ISD::TRAP, EVT::Other, Expand);
+  setOperationAction(ISD::TRAP, MVT::Other, Expand);
     
   IsLittleEndian = TD->isLittleEndian();
   UsesGlobalOffsetTable = false;
-  ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()).getSimpleVT();
-  memset(RegClassForVT, 0,EVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
+  ShiftAmountTy = PointerTy =
+      getValueType(TD->getIntPtrType()).getSimpleVT().SimpleTy;
+  memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
   memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
   maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
   allowUnalignedMemoryAccesses = false;
@@ -524,7 +525,7 @@ TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof)
   // Tell Legalize whether the assembler supports DEBUG_LOC.
   const TargetAsmInfo *TASM = TM.getTargetAsmInfo();
   if (!TASM || !TASM->hasDotLocAndDotFile())
-    setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
+    setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
 }
 
 TargetLowering::~TargetLowering() {
@@ -534,31 +535,31 @@ TargetLowering::~TargetLowering() {
 /// computeRegisterProperties - Once all of the register classes are added,
 /// this allows us to compute derived properties we expose.
 void TargetLowering::computeRegisterProperties() {
-  assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE &&
+  assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
          "Too many value types for ValueTypeActions to hold!");
 
   // Everything defaults to needing one register.
-  for (unsigned i = 0; i != EVT::LAST_VALUETYPE; ++i) {
+  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
     NumRegistersForVT[i] = 1;
-    RegisterTypeForVT[i] = TransformToType[i] = (EVT::SimpleValueType)i;
+    RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
   }
   // ...except isVoid, which doesn't need any registers.
-  NumRegistersForVT[EVT::isVoid] = 0;
+  NumRegistersForVT[MVT::isVoid] = 0;
 
   // Find the largest integer register class.
-  unsigned LargestIntReg = EVT::LAST_INTEGER_VALUETYPE;
+  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
   for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
-    assert(LargestIntReg != EVT::i1 && "No integer registers defined!");
+    assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
 
   // Every integer value type larger than this largest register takes twice as
   // many registers to represent as the previous ValueType.
   for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
-    EVT EVT = (EVT::SimpleValueType)ExpandedReg;
+    EVT EVT = (MVT::SimpleValueType)ExpandedReg;
     if (!EVT.isInteger())
       break;
     NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
-    RegisterTypeForVT[ExpandedReg] = (EVT::SimpleValueType)LargestIntReg;
-    TransformToType[ExpandedReg] = (EVT::SimpleValueType)(ExpandedReg - 1);
+    RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
+    TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
     ValueTypeActions.setTypeAction(EVT, Expand);
   }
 
@@ -566,54 +567,54 @@ void TargetLowering::computeRegisterProperties() {
   // register to see which ones need promotion.
   unsigned LegalIntReg = LargestIntReg;
   for (unsigned IntReg = LargestIntReg - 1;
-       IntReg >= (unsigned)EVT::i1; --IntReg) {
-    EVT IVT = (EVT::SimpleValueType)IntReg;
+       IntReg >= (unsigned)MVT::i1; --IntReg) {
+    EVT IVT = (MVT::SimpleValueType)IntReg;
     if (isTypeLegal(IVT)) {
       LegalIntReg = IntReg;
     } else {
       RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
-        (EVT::SimpleValueType)LegalIntReg;
+        (MVT::SimpleValueType)LegalIntReg;
       ValueTypeActions.setTypeAction(IVT, Promote);
     }
   }
 
   // ppcf128 type is really two f64's.
-  if (!isTypeLegal(EVT::ppcf128)) {
-    NumRegistersForVT[EVT::ppcf128] = 2*NumRegistersForVT[EVT::f64];
-    RegisterTypeForVT[EVT::ppcf128] = EVT::f64;
-    TransformToType[EVT::ppcf128] = EVT::f64;
-    ValueTypeActions.setTypeAction(EVT::ppcf128, Expand);
+  if (!isTypeLegal(MVT::ppcf128)) {
+    NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
+    RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
+    TransformToType[MVT::ppcf128] = MVT::f64;
+    ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
   }    
 
   // Decide how to handle f64. If the target does not have native f64 support,
   // expand it to i64 and we will be generating soft float library calls.
-  if (!isTypeLegal(EVT::f64)) {
-    NumRegistersForVT[EVT::f64] = NumRegistersForVT[EVT::i64];
-    RegisterTypeForVT[EVT::f64] = RegisterTypeForVT[EVT::i64];
-    TransformToType[EVT::f64] = EVT::i64;
-    ValueTypeActions.setTypeAction(EVT::f64, Expand);
+  if (!isTypeLegal(MVT::f64)) {
+    NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
+    RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
+    TransformToType[MVT::f64] = MVT::i64;
+    ValueTypeActions.setTypeAction(MVT::f64, Expand);
   }
 
   // Decide how to handle f32. If the target does not have native support for
   // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
-  if (!isTypeLegal(EVT::f32)) {
-    if (isTypeLegal(EVT::f64)) {
-      NumRegistersForVT[EVT::f32] = NumRegistersForVT[EVT::f64];
-      RegisterTypeForVT[EVT::f32] = RegisterTypeForVT[EVT::f64];
-      TransformToType[EVT::f32] = EVT::f64;
-      ValueTypeActions.setTypeAction(EVT::f32, Promote);
+  if (!isTypeLegal(MVT::f32)) {
+    if (isTypeLegal(MVT::f64)) {
+      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
+      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
+      TransformToType[MVT::f32] = MVT::f64;
+      ValueTypeActions.setTypeAction(MVT::f32, Promote);
     } else {
-      NumRegistersForVT[EVT::f32] = NumRegistersForVT[EVT::i32];
-      RegisterTypeForVT[EVT::f32] = RegisterTypeForVT[EVT::i32];
-      TransformToType[EVT::f32] = EVT::i32;
-      ValueTypeActions.setTypeAction(EVT::f32, Expand);
+      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
+      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
+      TransformToType[MVT::f32] = MVT::i32;
+      ValueTypeActions.setTypeAction(MVT::f32, Expand);
     }
   }
   
   // Loop over all of the vector value types to see which need transformations.
-  for (unsigned i = EVT::FIRST_VECTOR_VALUETYPE;
-       i <= (unsigned)EVT::LAST_VECTOR_VALUETYPE; ++i) {
-    EVT VT = (EVT::SimpleValueType)i;
+  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
+       i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
+    EVT VT = (MVT::SimpleValueType)i;
     if (!isTypeLegal(VT)) {
       EVT IntermediateVT, RegisterVT;
       unsigned NumIntermediates;
@@ -627,8 +628,8 @@ void TargetLowering::computeRegisterProperties() {
       bool IsLegalWiderType = false;
       EVT EltVT = VT.getVectorElementType();
       unsigned NElts = VT.getVectorNumElements();
-      for (unsigned nVT = i+1; nVT <= EVT::LAST_VECTOR_VALUETYPE; ++nVT) {
-        EVT SVT = (EVT::SimpleValueType)nVT;
+      for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
+        EVT SVT = (MVT::SimpleValueType)nVT;
         if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
             SVT.getVectorNumElements() > NElts) {
           TransformToType[i] = SVT;
@@ -641,7 +642,7 @@ void TargetLowering::computeRegisterProperties() {
         EVT NVT = VT.getPow2VectorType();
         if (NVT == VT) {
           // Type is already a power of 2.  The default action is to split.
-          TransformToType[i] = EVT::Other;
+          TransformToType[i] = MVT::Other;
           ValueTypeActions.setTypeAction(VT, Expand);
         } else {
           TransformToType[i] = NVT;
@@ -657,15 +658,15 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
 }
 
 
-EVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
-  return getValueType(TD->getIntPtrType()).getSimpleVT();
+MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
+  return getValueType(TD->getIntPtrType()).getSimpleVT().SimpleTy;
 }
 
 
 /// getVectorTypeBreakdown - Vector types are broken down into some number of
-/// legal first class types.  For example, EVT::v8f32 maps to 2 EVT::v4f32
-/// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
-/// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
+/// legal first class types.  For example, MVT::v8f32 maps to 2 MVT::v4f32
+/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
+/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
 ///
 /// This method returns the number of registers needed, and the VT for each
 /// register.  It also returns the VT and quantity of the intermediate values
@@ -718,7 +719,7 @@ unsigned TargetLowering::getVectorTypeBreakdown(EVT VT,
 
 /// getWidenVectorType: given a vector type, returns the type to widen to
 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
-/// If there is no vector type that we want to widen to, returns EVT::Other
+/// If there is no vector type that we want to widen to, returns MVT::Other
 /// When and where to widen is target dependent based on the cost of
 /// scalarizing vs using the wider vector type.
 EVT TargetLowering::getWidenVectorType(EVT VT) const {
@@ -727,7 +728,7 @@ EVT TargetLowering::getWidenVectorType(EVT VT) const {
     return VT;
  
   // Default is not to widen until moved to LegalizeTypes
-  return EVT::Other;
+  return MVT::Other;
 }
 
 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
@@ -1393,8 +1394,8 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
     // If this is an FP->Int bitcast and if the sign bit is the only thing that
     // is demanded, turn this into a FGETSIGN.
     if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
-        EVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
-        !EVT::isVector(Op.getOperand(0).getValueType())) {
+        MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
+        !MVT::isVector(Op.getOperand(0).getValueType())) {
       // Only do this xform if FGETSIGN is valid or if before legalize.
       if (!TLO.AfterLegalize ||
           isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
@@ -2010,46 +2011,46 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
 
   // Fold away ALL boolean setcc's.
   SDValue Temp;
-  if (N0.getValueType() == EVT::i1 && foldBooleans) {
+  if (N0.getValueType() == MVT::i1 && foldBooleans) {
     switch (Cond) {
     default: llvm_unreachable("Unknown integer setcc!");
     case ISD::SETEQ:  // X == Y  -> ~(X^Y)
-      Temp = DAG.getNode(ISD::XOR, dl, EVT::i1, N0, N1);
-      N0 = DAG.getNOT(dl, Temp, EVT::i1);
+      Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
+      N0 = DAG.getNOT(dl, Temp, MVT::i1);
       if (!DCI.isCalledByLegalizer())
         DCI.AddToWorklist(Temp.getNode());
       break;
     case ISD::SETNE:  // X != Y   -->  (X^Y)
-      N0 = DAG.getNode(ISD::XOR, dl, EVT::i1, N0, N1);
+      N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
       break;
     case ISD::SETGT:  // X >s Y   -->  X == 0 & Y == 1  -->  ~X & Y
     case ISD::SETULT: // X <u Y   -->  X == 0 & Y == 1  -->  ~X & Y
-      Temp = DAG.getNOT(dl, N0, EVT::i1);
-      N0 = DAG.getNode(ISD::AND, dl, EVT::i1, N1, Temp);
+      Temp = DAG.getNOT(dl, N0, MVT::i1);
+      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
       if (!DCI.isCalledByLegalizer())
         DCI.AddToWorklist(Temp.getNode());
       break;
     case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  ~Y & X
     case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  ~Y & X
-      Temp = DAG.getNOT(dl, N1, EVT::i1);
-      N0 = DAG.getNode(ISD::AND, dl, EVT::i1, N0, Temp);
+      Temp = DAG.getNOT(dl, N1, MVT::i1);
+      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
       if (!DCI.isCalledByLegalizer())
         DCI.AddToWorklist(Temp.getNode());
       break;
     case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  ~X | Y
     case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  ~X | Y
-      Temp = DAG.getNOT(dl, N0, EVT::i1);
-      N0 = DAG.getNode(ISD::OR, dl, EVT::i1, N1, Temp);
+      Temp = DAG.getNOT(dl, N0, MVT::i1);
+      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
       if (!DCI.isCalledByLegalizer())
         DCI.AddToWorklist(Temp.getNode());
       break;
     case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  ~Y | X
     case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  ~Y | X
-      Temp = DAG.getNOT(dl, N1, EVT::i1);
-      N0 = DAG.getNode(ISD::OR, dl, EVT::i1, N0, Temp);
+      Temp = DAG.getNOT(dl, N1, MVT::i1);
+      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
       break;
     }
-    if (VT != EVT::i1) {
+    if (VT != MVT::i1) {
       if (!DCI.isCalledByLegalizer())
         DCI.AddToWorklist(N0.getNode());
       // FIXME: If running after legalize, we probably can't do this.
@@ -2245,7 +2246,7 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
         // now; without this it would get ZExt'd later in
         // ScheduleDAGSDNodes::EmitNode, which is very generic.
         Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
-                                            EVT::i64));
+                                            MVT::i64));
         return;
       }
     }