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authorJakob Stoklund Olesen <stoklund@2pi.dk>2012-08-07 22:47:06 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2012-08-07 22:47:06 +0000
commit8c5c0733cde7c941de6c9386a07a8378c5c482c5 (patch)
treeb9c63a68ee8a8d2c23b127b8ab8e8a564433e250 /lib/CodeGen/TwoAddressInstructionPass.cpp
parent74500bdba3eae36a1a8a17d8bad0b971b9c212ec (diff)
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Skip tied operand pairs that already have the same register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161454 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/TwoAddressInstructionPass.cpp')
-rw-r--r--lib/CodeGen/TwoAddressInstructionPass.cpp21
1 files changed, 11 insertions, 10 deletions
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index 62d54208c6..d22274496a 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -1209,27 +1209,28 @@ collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
continue;
AnyOps = true;
+ MachineOperand &SrcMO = MI->getOperand(SrcIdx);
+ MachineOperand &DstMO = MI->getOperand(DstIdx);
+ unsigned SrcReg = SrcMO.getReg();
+ unsigned DstReg = DstMO.getReg();
+ // Tied constraint already satisfied?
+ if (SrcReg == DstReg)
+ continue;
- assert(MI->getOperand(SrcIdx).isReg() &&
- MI->getOperand(SrcIdx).getReg() &&
- MI->getOperand(SrcIdx).isUse() &&
- "two address instruction invalid");
-
- unsigned RegB = MI->getOperand(SrcIdx).getReg();
+ assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
// Deal with <undef> uses immediately - simply rewrite the src operand.
- if (MI->getOperand(SrcIdx).isUndef()) {
- unsigned DstReg = MI->getOperand(DstIdx).getReg();
+ if (SrcMO.isUndef()) {
// Constrain the DstReg register class if required.
if (TargetRegisterInfo::isVirtualRegister(DstReg))
if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
TRI, *MF))
MRI->constrainRegClass(DstReg, RC);
- MI->getOperand(SrcIdx).setReg(DstReg);
+ SrcMO.setReg(DstReg);
DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
continue;
}
- TiedOperands[RegB].push_back(std::make_pair(SrcIdx, DstIdx));
+ TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
}
return AnyOps;
}