Removed tabs everywhere except autogenerated & external files. Add make

target for tabs checking.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 47 insertions, 47 deletions

diff --git a/lib/CodeGen/MachOWriter.h b/lib/CodeGen/MachOWriter.h
index 061213a8c8..0792ac8a7d 100644
--- a/lib/CodeGen/MachOWriter.h
+++ b/lib/CodeGen/MachOWriter.h
@@ -254,19 +254,19 @@ namespace llvm {
       // The following constants are getting pulled in by one of the
       // system headers, which creates a neat clash with the enum.
 #if !defined(VM_PROT_NONE)
-#define VM_PROT_NONE		0x00
+#define VM_PROT_NONE    0x00
 #endif
 #if !defined(VM_PROT_READ)
-#define VM_PROT_READ		0x01
+#define VM_PROT_READ    0x01
 #endif
 #if !defined(VM_PROT_WRITE)
-#define VM_PROT_WRITE		0x02
+#define VM_PROT_WRITE   0x02
 #endif
 #if !defined(VM_PROT_EXECUTE)
-#define VM_PROT_EXECUTE		0x04
+#define VM_PROT_EXECUTE 0x04
 #endif
 #if !defined(VM_PROT_ALL)
-#define VM_PROT_ALL		0x07
+#define VM_PROT_ALL     0x07
 #endif
 
       // Constants for the vm protection fields
diff --git a/lib/CodeGen/README.txt b/lib/CodeGen/README.txt
index aa5a54c3ba..8e6b0a5e46 100644
--- a/lib/CodeGen/README.txt
+++ b/lib/CodeGen/README.txt
@@ -2,29 +2,29 @@
 
 Common register allocation / spilling problem:
 
-	mul lr, r4, lr
-	str lr, [sp, #+52]
-	ldr lr, [r1, #+32]
-	sxth r3, r3
-	ldr r4, [sp, #+52]
-	mla r4, r3, lr, r4
+        mul lr, r4, lr
+        str lr, [sp, #+52]
+        ldr lr, [r1, #+32]
+        sxth r3, r3
+        ldr r4, [sp, #+52]
+        mla r4, r3, lr, r4
 
 can be:
 
-	mul lr, r4, lr
+        mul lr, r4, lr
         mov r4, lr
-	str lr, [sp, #+52]
-	ldr lr, [r1, #+32]
-	sxth r3, r3
-	mla r4, r3, lr, r4
+        str lr, [sp, #+52]
+        ldr lr, [r1, #+32]
+        sxth r3, r3
+        mla r4, r3, lr, r4
 
 and then "merge" mul and mov:
 
-	mul r4, r4, lr
-	str lr, [sp, #+52]
-	ldr lr, [r1, #+32]
-	sxth r3, r3
-	mla r4, r3, lr, r4
+        mul r4, r4, lr
+        str lr, [sp, #+52]
+        ldr lr, [r1, #+32]
+        sxth r3, r3
+        mla r4, r3, lr, r4
 
 It also increase the likelyhood the store may become dead.
 
@@ -70,13 +70,13 @@ Some potential added complexities:
 
 bb27 ...
         ...
-	%reg1037 = ADDri %reg1039, 1
-	%reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
+        %reg1037 = ADDri %reg1039, 1
+        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
     Successors according to CFG: 0x8b03bf0 (#5)
 
 bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
     Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
-	%reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>
+        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>
 
 Note ADDri is not a two-address instruction. However, its result %reg1037 is an
 operand of the PHI node in bb76 and its operand %reg1039 is the result of the
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
index e4133cec6e..c6187f1109 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
@@ -288,9 +288,9 @@ private:
                                         // Tally iterator 
   
   /// SlotsAvailable - Returns true if all units are available.
-	///
+  ///
   bool SlotsAvailable(Iter Begin, unsigned N, unsigned ResourceSet,
-                                              unsigned &Resource) {
+                      unsigned &Resource) {
     assert(N && "Must check availability with N != 0");
     // Determine end of interval
     Iter End = Begin + N;
@@ -318,23 +318,23 @@ private:
     Resource = 0;
     return false;
   }
-	
-	/// RetrySlot - Finds a good candidate slot to retry search.
+  
+  /// RetrySlot - Finds a good candidate slot to retry search.
   Iter RetrySlot(Iter Begin, unsigned N, unsigned ResourceSet) {
     assert(N && "Must check availability with N != 0");
     // Determine end of interval
     Iter End = Begin + N;
     assert(End <= Tally.end() && "Tally is not large enough for schedule");
-		
-		while (Begin != End--) {
-			// Clear units in use
-			ResourceSet &= ~*End;
-			// If no units left then we should go no further 
-			if (!ResourceSet) return End + 1;
-		}
-		// Made it all the way through
-		return Begin;
-	}
+    
+    while (Begin != End--) {
+      // Clear units in use
+      ResourceSet &= ~*End;
+      // If no units left then we should go no further 
+      if (!ResourceSet) return End + 1;
+    }
+    // Made it all the way through
+    return Begin;
+  }
   
   /// FindAndReserveStages - Return true if the stages can be completed. If
   /// so mark as busy.
@@ -391,13 +391,13 @@ public:
   // FindAndReserve - Locate an ideal slot for the specified stages and mark
   // as busy.
   unsigned FindAndReserve(unsigned Slot, InstrStage *StageBegin,
-                                         InstrStage *StageEnd) {
-		// Where to begin 
-		Iter Begin = Tally.begin() + Slot;
-		// Find a free slot
-		Iter Where = FindSlots(Begin, StageBegin, StageEnd);
-		// Distance is slot number
-		unsigned Final = Where - Tally.begin();
+                          InstrStage *StageEnd) {
+    // Where to begin 
+    Iter Begin = Tally.begin() + Slot;
+    // Find a free slot
+    Iter Where = FindSlots(Begin, StageBegin, StageEnd);
+    // Distance is slot number
+    unsigned Final = Where - Tally.begin();
     return Final;
   }
 
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index d72c6eb01d..7d30062995 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -2150,7 +2150,7 @@ static mu magicu64(uint64_t d)
 /// multiplying by a magic number.  See:
 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
 SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 
-				    std::vector<SDNode*>* Created) const {
+                                    std::vector<SDNode*>* Created) const {
   MVT::ValueType VT = N->getValueType(0);
   
   // Check to see if we can do this.
@@ -2198,7 +2198,7 @@ SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
 /// multiplying by a magic number.  See:
 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
 SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
-				    std::vector<SDNode*>* Created) const {
+                                    std::vector<SDNode*>* Created) const {
   MVT::ValueType VT = N->getValueType(0);
   
   // Check to see if we can do this.