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author | Juergen Ributzka <juergen@apple.com> | 2013-11-19 00:57:56 +0000 |
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committer | Juergen Ributzka <juergen@apple.com> | 2013-11-19 00:57:56 +0000 |
commit | 354362524a72b3fa43a6c09380b7ae3b2380cbba (patch) | |
tree | db9821d531f3ec0554d83400221f54e4e322877b /lib/CodeGen | |
parent | 26efdc5621043d28dc0c78addc7b7a75d1591a10 (diff) | |
download | llvm-354362524a72b3fa43a6c09380b7ae3b2380cbba.tar.gz llvm-354362524a72b3fa43a6c09380b7ae3b2380cbba.tar.bz2 llvm-354362524a72b3fa43a6c09380b7ae3b2380cbba.tar.xz |
[weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r-- | lib/CodeGen/MachineRegisterInfo.cpp | 3 | ||||
-rw-r--r-- | lib/CodeGen/MachineScheduler.cpp | 4 | ||||
-rw-r--r-- | lib/CodeGen/RegAllocBase.cpp | 3 | ||||
-rw-r--r-- | lib/CodeGen/RegAllocBase.h | 1 |
4 files changed, 11 insertions, 0 deletions
diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp index ce7d567cc2..f8b8796b25 100644 --- a/lib/CodeGen/MachineRegisterInfo.cpp +++ b/lib/CodeGen/MachineRegisterInfo.cpp @@ -19,6 +19,9 @@ using namespace llvm; +// Pin the vtable to this file. +void MachineRegisterInfo::Delegate::anchor() {} + MachineRegisterInfo::MachineRegisterInfo(const TargetMachine &TM) : TM(TM), TheDelegate(0), IsSSA(true), TracksLiveness(true) { VRegInfo.reserve(256); diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp index 3144dfe4d3..e71c4df0b7 100644 --- a/lib/CodeGen/MachineScheduler.cpp +++ b/lib/CodeGen/MachineScheduler.cpp @@ -72,6 +72,10 @@ static cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden, // DAG subtrees must have at least this many nodes. static const unsigned MinSubtreeSize = 8; +// Pin the vtables to this file. +void MachineSchedStrategy::anchor() {} +void ScheduleDAGMutation::anchor() {} + //===----------------------------------------------------------------------===// // Machine Instruction Scheduling Pass and Registry //===----------------------------------------------------------------------===// diff --git a/lib/CodeGen/RegAllocBase.cpp b/lib/CodeGen/RegAllocBase.cpp index b94ce4d33f..293e306a29 100644 --- a/lib/CodeGen/RegAllocBase.cpp +++ b/lib/CodeGen/RegAllocBase.cpp @@ -50,6 +50,9 @@ bool RegAllocBase::VerifyEnabled = false; // RegAllocBase Implementation //===----------------------------------------------------------------------===// +// Pin the vtable to this file. +void RegAllocBase::anchor() {} + void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat) { diff --git a/lib/CodeGen/RegAllocBase.h b/lib/CodeGen/RegAllocBase.h index 9c0029837d..c17a8d96ef 100644 --- a/lib/CodeGen/RegAllocBase.h +++ b/lib/CodeGen/RegAllocBase.h @@ -57,6 +57,7 @@ class Spiller; /// live range splitting. They must also override enqueue/dequeue to provide an /// assignment order. class RegAllocBase { + virtual void anchor(); protected: const TargetRegisterInfo *TRI; MachineRegisterInfo *MRI; |