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author | David Goodwin <david_goodwin@apple.com> | 2009-11-05 01:19:35 +0000 |
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committer | David Goodwin <david_goodwin@apple.com> | 2009-11-05 01:19:35 +0000 |
commit | 54097836f31660bd5e84c34ee8c92d237844315f (patch) | |
tree | 3cade5142826b0a99e1ffd48b60cfcffdf1b5747 /lib/CodeGen | |
parent | 090780be1c94163ad7cb9368fdb1b23714b2518e (diff) | |
download | llvm-54097836f31660bd5e84c34ee8c92d237844315f.tar.gz llvm-54097836f31660bd5e84c34ee8c92d237844315f.tar.bz2 llvm-54097836f31660bd5e84c34ee8c92d237844315f.tar.xz |
Break anti-dependencies using free registers in a round-robin manner to avoid introducing new anti-dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86098 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r-- | lib/CodeGen/AggressiveAntiDepBreaker.cpp | 57 | ||||
-rw-r--r-- | lib/CodeGen/AggressiveAntiDepBreaker.h | 4 | ||||
-rw-r--r-- | lib/CodeGen/PostRASchedulerList.cpp | 6 |
3 files changed, 49 insertions, 18 deletions
diff --git a/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/lib/CodeGen/AggressiveAntiDepBreaker.cpp index ffb6315427..416d6741bb 100644 --- a/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -491,8 +491,9 @@ BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) { } bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( - unsigned AntiDepGroupIndex, - std::map<unsigned, unsigned> &RenameMap) { + unsigned AntiDepGroupIndex, + RenameOrderType& RenameOrder, + std::map<unsigned, unsigned> &RenameMap) { unsigned *KillIndices = State->GetKillIndices(); unsigned *DefIndices = State->GetDefIndices(); std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>& @@ -547,22 +548,41 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( if (Regs.size() > 1) return false; - // Check each possible rename register for SuperReg. If that register - // is available, and the corresponding registers are available for - // the other group subregisters, then we can use those registers to - // rename. - DEBUG(errs() << "\tFind Register:"); + // Check each possible rename register for SuperReg in round-robin + // order. If that register is available, and the corresponding + // registers are available for the other group subregisters, then we + // can use those registers to rename. BitVector SuperBV = RenameRegisterMap[SuperReg]; - for (int r = SuperBV.find_first(); r != -1; r = SuperBV.find_next(r)) { - const unsigned Reg = (unsigned)r; + const TargetRegisterClass *SuperRC = + TRI->getPhysicalRegisterRegClass(SuperReg, MVT::Other); + + const TargetRegisterClass::iterator RB = SuperRC->allocation_order_begin(MF); + const TargetRegisterClass::iterator RE = SuperRC->allocation_order_end(MF); + if (RB == RE) { + DEBUG(errs() << "\tEmpty Regclass!!\n"); + return false; + } + + if (RenameOrder.count(SuperRC) == 0) + RenameOrder.insert(RenameOrderType::value_type(SuperRC, RE)); + + DEBUG(errs() << "\tFind Register:"); + + const TargetRegisterClass::iterator OrigR = RenameOrder.at(SuperRC); + const TargetRegisterClass::iterator EndR = ((OrigR == RE) ? RB : OrigR); + TargetRegisterClass::iterator R = OrigR; + do { + if (R == RB) R = RE; + --R; + const unsigned Reg = *R; // Don't replace a register with itself. if (Reg == SuperReg) continue; - + DEBUG(errs() << " " << TRI->getName(Reg)); - + // If Reg is dead and Reg's most recent def is not before - // SuperRegs's kill, it's safe to replace SuperReg with - // Reg. We must also check all subregisters of Reg. + // SuperRegs's kill, it's safe to replace SuperReg with Reg. We + // must also check all subregisters of Reg. if (State->IsLive(Reg) || (KillIndices[SuperReg] > DefIndices[Reg])) { DEBUG(errs() << "(live)"); continue; @@ -580,13 +600,15 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( if (found) continue; } - + if (Reg != 0) { DEBUG(errs() << '\n'); + RenameOrder.erase(SuperRC); + RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); RenameMap.insert(std::pair<unsigned, unsigned>(SuperReg, Reg)); return true; } - } + } while (R != EndR); DEBUG(errs() << '\n'); @@ -627,6 +649,9 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( State = new AggressiveAntiDepState(*SavedState); } } + + // For each regclass the next register to use for renaming. + RenameOrderType RenameOrder; // ...need a map from MI to SUnit. std::map<MachineInstr *, SUnit *> MISUnitMap; @@ -738,7 +763,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( // Look for a suitable register to use to break the anti-dependence. std::map<unsigned, unsigned> RenameMap; - if (FindSuitableFreeRegisters(GroupIndex, RenameMap)) { + if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) { DEBUG(errs() << "\tBreaking anti-dependence edge on " << TRI->getName(AntiDepReg) << ":"); diff --git a/lib/CodeGen/AggressiveAntiDepBreaker.h b/lib/CodeGen/AggressiveAntiDepBreaker.h index 5d9b40b00c..c5121682bd 100644 --- a/lib/CodeGen/AggressiveAntiDepBreaker.h +++ b/lib/CodeGen/AggressiveAntiDepBreaker.h @@ -155,6 +155,9 @@ namespace llvm { void FinishBlock(); private: + typedef std::map<const TargetRegisterClass *, + TargetRegisterClass::const_iterator> RenameOrderType; + /// IsImplicitDefUse - Return true if MO represents a register /// that is both implicitly used and defined in MI bool IsImplicitDefUse(MachineInstr *MI, MachineOperand& MO); @@ -169,6 +172,7 @@ namespace llvm { void ScanInstruction(MachineInstr *MI, unsigned Count); BitVector GetRenameRegisters(unsigned Reg); bool FindSuitableFreeRegisters(unsigned AntiDepGroupIndex, + RenameOrderType& RenameOrder, std::map<unsigned, unsigned> &RenameMap); }; } diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index d5edb36b44..3ed61a267f 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -770,7 +770,8 @@ void SchedulePostRATDList::ListScheduleTopDown( // just advance the current cycle and try again. DEBUG(errs() << "*** Stall in cycle " << CurCycle << '\n'); HazardRec->AdvanceCycle(); - ++NumStalls; + if (!IgnoreAntiDep) + ++NumStalls; } else { // Otherwise, we have no instructions to issue and we have instructions // that will fault if we don't do this right. This is the case for @@ -778,7 +779,8 @@ void SchedulePostRATDList::ListScheduleTopDown( DEBUG(errs() << "*** Emitting noop in cycle " << CurCycle << '\n'); HazardRec->EmitNoop(); Sequence.push_back(0); // NULL here means noop - ++NumNoops; + if (!IgnoreAntiDep) + ++NumNoops; } ++CurCycle; |