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authorChad Rosier <mcrosier@codeaurora.org>2013-10-08 20:43:30 +0000
committerChad Rosier <mcrosier@codeaurora.org>2013-10-08 20:43:30 +0000
commit3dfe644f7b6a560e1991b03d8c419c973ac7ed8d (patch)
tree2d8a4e016b24fa61e59501defc94d761acec190d /lib/Target/AArch64/AArch64InstrFormats.td
parent73f615b0bd822db3a2a8aab2fd4ed58f093c9769 (diff)
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[AArch64] Add support for NEON scalar signed/unsigned integer to floating-point
convert instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192231 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64InstrFormats.td')
-rw-r--r--lib/Target/AArch64/AArch64InstrFormats.td16
1 files changed, 16 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td
index fb87db605d..5781578a55 100644
--- a/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1178,5 +1178,21 @@ class NeonI_2VAcross<bit q, bit u, bits<2> size, bits<5> opcode,
// Inherit Rd in 4-0
}
+// Format AdvSIMD scalar two registers miscellaneous
+class NeonI_Scalar2SameMisc<bit u, bits<2> size, bits<5> opcode, dag outs, dag ins,
+ string asmstr, list<dag> patterns, InstrItinClass itin>
+ : A64InstRdn<outs, ins, asmstr, patterns, itin> {
+ let Inst{31} = 0b0;
+ let Inst{30} = 0b1;
+ let Inst{29} = u;
+ let Inst{28-24} = 0b11110;
+ let Inst{23-22} = size;
+ let Inst{21-17} = 0b10000;
+ let Inst{16-12} = opcode;
+ let Inst{11-10} = 0b10;
+ // Inherit Rn in 9-5
+ // Inherit Rd in 4-0
+}
+
}