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author | Hao Liu <Hao.Liu@arm.com> | 2013-11-05 03:39:32 +0000 |
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committer | Hao Liu <Hao.Liu@arm.com> | 2013-11-05 03:39:32 +0000 |
commit | 591c2f738a3e12026ff5504a486d54fc21fb3049 (patch) | |
tree | 6909db3910a1e52022a3166d0b2d7648269f5bc3 /lib/Target/AArch64/AArch64InstrFormats.td | |
parent | 8263dcdf23bc534405745959c97cbfd562362458 (diff) | |
download | llvm-591c2f738a3e12026ff5504a486d54fc21fb3049.tar.gz llvm-591c2f738a3e12026ff5504a486d54fc21fb3049.tar.bz2 llvm-591c2f738a3e12026ff5504a486d54fc21fb3049.tar.xz |
Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64InstrFormats.td')
-rw-r--r-- | lib/Target/AArch64/AArch64InstrFormats.td | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td index 44dbc9d540..4782b55de0 100644 --- a/lib/Target/AArch64/AArch64InstrFormats.td +++ b/lib/Target/AArch64/AArch64InstrFormats.td @@ -120,6 +120,14 @@ class A64InstRdnm<dag outs, dag ins, string asmstr, let Inst{20-16} = Rm; } +class A64InstRtnm<dag outs, dag ins, string asmstr, + list<dag> patterns, InstrItinClass itin> + : A64InstRtn<outs, ins, asmstr, patterns, itin> { + bits<5> Rm; + + let Inst{20-16} = Rm; +} + //===----------------------------------------------------------------------===// // // Actual A64 Instruction Formats @@ -1216,6 +1224,24 @@ class NeonI_LdStMult<bit q, bit l, bits<4> opcode, bits<2> size, // Inherit Rt in 4-0 } +// Format AdvSIMD vector load/store multiple N-element structure (post-index) +class NeonI_LdStMult_Post<bit q, bit l, bits<4> opcode, bits<2> size, + dag outs, dag ins, string asmstr, + list<dag> patterns, InstrItinClass itin> + : A64InstRtnm<outs, ins, asmstr, patterns, itin> +{ + let Inst{31} = 0b0; + let Inst{30} = q; + let Inst{29-23} = 0b0011001; + let Inst{22} = l; + let Inst{21} = 0b0; + // Inherit Rm in 20-16 + let Inst{15-12} = opcode; + let Inst{11-10} = size; + // Inherit Rn in 9-5 + // Inherit Rt in 4-0 +} + // Format AdvSIMD 3 scalar registers with different type class NeonI_Scalar3Diff<bit u, bits<2> size, bits<4> opcode, |