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| author | Tim Northover <Tim.Northover@arm.com> | 2013-02-14 16:22:14 +0000 |
|---|---|---|
| committer | Tim Northover <Tim.Northover@arm.com> | 2013-02-14 16:22:14 +0000 |
| commit | 5464c301c4472f54f700e171750fc51d39a0f4b8 (patch) | |
| tree | 29e5596d881d274a1528ddb6d3dda6b0fcc0da4f /lib/Target/AArch64 | |
| parent | 5bd6cb2dabf3fea9cb9fa0b275fbc7ceb85ba970 (diff) | |
| download | llvm-5464c301c4472f54f700e171750fc51d39a0f4b8.tar.gz llvm-5464c301c4472f54f700e171750fc51d39a0f4b8.tar.bz2 llvm-5464c301c4472f54f700e171750fc51d39a0f4b8.tar.xz | |
AArch64: stop claiming that NEON registers are usable for now.
If vector types have legal register classes, then LLVM bypasses LegalizeTypes
on them, which causes faults currently since the code to handle them isn't in
place.
This fixes test failures when AArch64 is the default target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175172 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64')
| -rw-r--r-- | lib/Target/AArch64/AArch64ISelLowering.cpp | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index ff28dc17fd..2c11547c46 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -57,17 +57,6 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM) addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); - // And the vectors - addRegisterClass(MVT::v8i8, &AArch64::VPR64RegClass); - addRegisterClass(MVT::v4i16, &AArch64::VPR64RegClass); - addRegisterClass(MVT::v2i32, &AArch64::VPR64RegClass); - addRegisterClass(MVT::v2f32, &AArch64::VPR64RegClass); - addRegisterClass(MVT::v16i8, &AArch64::VPR128RegClass); - addRegisterClass(MVT::v8i16, &AArch64::VPR128RegClass); - addRegisterClass(MVT::v4i32, &AArch64::VPR128RegClass); - addRegisterClass(MVT::v4f32, &AArch64::VPR128RegClass); - addRegisterClass(MVT::v2f64, &AArch64::VPR128RegClass); - computeRegisterProperties(); // Some atomic operations can be folded into load-acquire or store-release |