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authorBill Wendling <isanbard@gmail.com>2013-12-01 04:36:39 +0000
committerBill Wendling <isanbard@gmail.com>2013-12-01 04:36:39 +0000
commitae38e1a9b485dcbeddac0ac9530c195e387cafe3 (patch)
tree871fa64ece0f69fa97b2577d4c6b11464e23885e /lib/Target/AArch64
parent53873c844f904b0197e6a917844f438d86684e30 (diff)
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Merging r195903:
------------------------------------------------------------------------ r195903 | haoliu | 2013-11-27 17:07:45 -0800 (Wed, 27 Nov 2013) | 2 lines AArch64: Fix a bug about disassembling post-index load single element to 4 vectors ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196025 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64')
-rw-r--r--lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 65f477642d..1f70a3d32c 100644
--- a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -1342,13 +1342,13 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: {
switch (Opc) {
case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
- TransferBytes = 3; break;
+ TransferBytes = 4; break;
case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register:
- TransferBytes = 6; break;
+ TransferBytes = 8; break;
case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register:
- TransferBytes = 12; break;
+ TransferBytes = 16; break;
case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register:
- TransferBytes = 24; break;
+ TransferBytes = 32; break;
}
IsLoad = true;
NumVecs = 4;