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| author | Bill Wendling <isanbard@gmail.com> | 2013-12-08 00:07:48 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2013-12-08 00:07:48 +0000 |
| commit | f04a4d74b86733b853b7445ab6d5a3bde025a30d (patch) | |
| tree | dde98b9a0e589c10e128ca9b58a336e934cd85d9 /lib/Target/AArch64 | |
| parent | 488aab6df3723d49e256042b99e5ef2f5a9cf46b (diff) | |
| download | llvm-f04a4d74b86733b853b7445ab6d5a3bde025a30d.tar.gz llvm-f04a4d74b86733b853b7445ab6d5a3bde025a30d.tar.bz2 llvm-f04a4d74b86733b853b7445ab6d5a3bde025a30d.tar.xz | |
Merging r196456:
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r196456 | jiangning | 2013-12-04 18:12:01 -0800 (Wed, 04 Dec 2013) | 2 lines
For AArch64, add missing register cost calculation for big value types like v4i64 and v8i64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196700 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64')
| -rw-r--r-- | lib/Target/AArch64/AArch64ISelLowering.cpp | 25 | ||||
| -rw-r--r-- | lib/Target/AArch64/AArch64ISelLowering.h | 4 |
2 files changed, 28 insertions, 1 deletions
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 5d20a96ff0..8cc0886d95 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -66,7 +66,7 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM) addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass); addRegisterClass(MVT::v1f32, &AArch64::FPR32RegClass); addRegisterClass(MVT::v1f64, &AArch64::FPR64RegClass); - addRegisterClass(MVT::v8i8, &AArch64::FPR64RegClass); + addRegisterClass(MVT::v8i8, &AArch64::FPR64RegClass); addRegisterClass(MVT::v4i16, &AArch64::FPR64RegClass); addRegisterClass(MVT::v2i32, &AArch64::FPR64RegClass); addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass); @@ -403,6 +403,29 @@ static void getExclusiveOperation(unsigned Size, AtomicOrdering Ord, StrOpc = StoreOps[Log2_32(Size)]; } +// FIXME: AArch64::DTripleRegClass and AArch64::QTripleRegClass don't really +// have value type mapped, and they are both being defined as MVT::untyped. +// Without knowing the MVT type, MachineLICM::getRegisterClassIDAndCost +// would fail to figure out the register pressure correctly. +std::pair<const TargetRegisterClass*, uint8_t> +AArch64TargetLowering::findRepresentativeClass(MVT VT) const{ + const TargetRegisterClass *RRC = 0; + uint8_t Cost = 1; + switch (VT.SimpleTy) { + default: + return TargetLowering::findRepresentativeClass(VT); + case MVT::v4i64: + RRC = &AArch64::QPairRegClass; + Cost = 2; + break; + case MVT::v8i64: + RRC = &AArch64::QQuadRegClass; + Cost = 4; + break; + } + return std::make_pair(RRC, Cost); +} + MachineBasicBlock * AArch64TargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, diff --git a/lib/Target/AArch64/AArch64ISelLowering.h b/lib/Target/AArch64/AArch64ISelLowering.h index 4cc2135143..8ad5a79a33 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.h +++ b/lib/Target/AArch64/AArch64ISelLowering.h @@ -343,6 +343,10 @@ public: virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const LLVM_OVERRIDE; +protected: + std::pair<const TargetRegisterClass*, uint8_t> + findRepresentativeClass(MVT VT) const; + private: const InstrItineraryData *Itins; |