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| author | Bill Wendling <isanbard@gmail.com> | 2013-11-25 05:36:37 +0000 |
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| committer | Bill Wendling <isanbard@gmail.com> | 2013-11-25 05:36:37 +0000 |
| commit | fd76325f8afd780f3b5863a32d4a7f1bc88fec07 (patch) | |
| tree | 99f6e7278b1ac8a9140f1eda94162f3f2d14e1ba /lib/Target/AArch64 | |
| parent | fc1f9531d3f9bf14b4b20b80f158317795d3d1d8 (diff) | |
| download | llvm-fd76325f8afd780f3b5863a32d4a7f1bc88fec07.tar.gz llvm-fd76325f8afd780f3b5863a32d4a7f1bc88fec07.tar.bz2 llvm-fd76325f8afd780f3b5863a32d4a7f1bc88fec07.tar.xz | |
Merging r195514:
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r195514 | tstellar | 2013-11-22 15:07:58 -0800 (Fri, 22 Nov 2013) | 6 lines
R600/SI: Fixing handling of condition codes
We were ignoring the ordered/onordered bits and also the signed/unsigned
bits of condition codes when lowering the DAG to MachineInstrs.
NOTE: This is a candidate for the 3.4 branch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195609 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64')
0 files changed, 0 insertions, 0 deletions