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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-04-09 15:24:22 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-04-09 15:24:22 +0000 |
| commit | 0b71dafd66dba5eb9d438d6620f229d7aece0650 (patch) | |
| tree | e5dd4aff056350f189d68935b7a35b800fea00a4 /lib/Target/ARM/A15SDOptimizer.cpp | |
| parent | 79944ce3dad5d138e561e39af2103c17b79a90f0 (diff) | |
| download | llvm-0b71dafd66dba5eb9d438d6620f229d7aece0650.tar.gz llvm-0b71dafd66dba5eb9d438d6620f229d7aece0650.tar.bz2 llvm-0b71dafd66dba5eb9d438d6620f229d7aece0650.tar.xz | |
Merging r204304:
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r204304 | Hao.Liu | 2014-03-20 01:36:59 -0400 (Thu, 20 Mar 2014) | 2 lines
[ARM]Fix an assertion failure in A15SDOptimizer about DPair reg class by treating DPair as QPR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205904 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/A15SDOptimizer.cpp')
| -rw-r--r-- | lib/Target/ARM/A15SDOptimizer.cpp | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/lib/Target/ARM/A15SDOptimizer.cpp b/lib/Target/ARM/A15SDOptimizer.cpp index ff585b41a2..3e805a2b68 100644 --- a/lib/Target/ARM/A15SDOptimizer.cpp +++ b/lib/Target/ARM/A15SDOptimizer.cpp @@ -418,7 +418,8 @@ SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(MachineInstr *MI) { if (!MO.isReg() || !MO.isUse()) continue; if (!usesRegClass(MO, &ARM::DPRRegClass) && - !usesRegClass(MO, &ARM::QPRRegClass)) + !usesRegClass(MO, &ARM::QPRRegClass) && + !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR continue; Defs.push_back(MO.getReg()); @@ -538,7 +539,10 @@ A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) { InsertPt++; unsigned Out; - if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass)) { + // DPair has the same length as QPR and also has two DPRs as subreg. + // Treat DPair as QPR. + if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || + MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg, ARM::dsub_0, &ARM::DPRRegClass); unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg, @@ -571,7 +575,9 @@ A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) { default: llvm_unreachable("Unknown preferred lane!"); } - bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass); + // Treat DPair as QPR + bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) || + usesRegClass(MI->getOperand(0), &ARM::DPairRegClass); Out = createImplicitDef(MBB, InsertPt, DL); Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg); |