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| author | Evan Cheng <evan.cheng@apple.com> | 2012-12-20 19:59:30 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2012-12-20 19:59:30 +0000 |
| commit | 139e407d526193017d42473c8d4892933de78f14 (patch) | |
| tree | 37f08e11f0f3c4c2944880253feea017e2146aba /lib/Target/ARM/ARM.td | |
| parent | 15019a8814b7877367ca7bcd7d173710259f7c20 (diff) | |
| download | llvm-139e407d526193017d42473c8d4892933de78f14.tar.gz llvm-139e407d526193017d42473c8d4892933de78f14.tar.bz2 llvm-139e407d526193017d42473c8d4892933de78f14.tar.xz | |
On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,
are more expensive than the non-flag setting variant. Teach thumb2 size
reduction pass to avoid generating them unless we are optimizing for size.
rdar://12892707
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170728 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARM.td')
| -rw-r--r-- | lib/Target/ARM/ARM.td | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 5ea251a795..45a65fd6f1 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -89,6 +89,10 @@ def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", "AvoidCPSRPartialUpdate", "true", "Avoid CPSR partial update for OOO execution">; +def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", + "AvoidMOVsShifterOperand", "true", + "Avoid movs instructions with shifter operand">; + // Some processors perform return stack prediction. CodeGen should avoid issue // "normal" call instructions to callees which do not return. def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true", @@ -152,6 +156,7 @@ def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", [FeatureNEONForFP, FeatureT2XtPk, FeatureVFP4, FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureAvoidPartialCPSR, + FeatureAvoidMOVsShOp, FeatureHasSlowFPVMLx]>; // FIXME: It has not been determined if A15 has these features. |