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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-01 21:12:19 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-01 21:12:19 +0000 |
| commit | a7603982dbf9e240ecc7ed6eddcd1cdb868107ac (patch) | |
| tree | 87a983d92fb76b9bfbd27279864c36283ec030bc /lib/Target/ARM/ARM.td | |
| parent | 5b1b4489cf3a0f56f8be0673fc5cc380a32d277b (diff) | |
| download | llvm-a7603982dbf9e240ecc7ed6eddcd1cdb868107ac.tar.gz llvm-a7603982dbf9e240ecc7ed6eddcd1cdb868107ac.tar.bz2 llvm-a7603982dbf9e240ecc7ed6eddcd1cdb868107ac.tar.xz | |
ARMv7M vs. ARMv7E-M support.
The DSP instructions in the Thumb2 instruction set are an optional extension
in the Cortex-M* archtitecture. When present, the implementation is considered
an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation."
Add a subtarget feature hook for the v7e-m instructions and hook it up. The
cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is
a v7e-m implementation.
rdar://9572992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARM.td')
| -rw-r--r-- | lib/Target/ARM/ARM.td | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 6af5f85e8a..39a3528836 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -75,6 +75,10 @@ def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", "AvoidCPSRPartialUpdate", "true", "Avoid CPSR partial update for OOO execution">; +/// Some M architectures don't have the DSP extension (v7E-M vs. v7M) +def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true", + "Supports v7 DSP instructions in Thumb2.">; + // Multiprocessing extension. def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", "Supports Multiprocessing extension">; @@ -93,14 +97,20 @@ def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M", [FeatureNoARM, FeatureDB]>; def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2", "ARM v6t2", - [FeatureThumb2]>; + [FeatureThumb2, FeatureDSPThumb2]>; def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A", "ARM v7A", - [FeatureThumb2, FeatureNEON, FeatureDB]>; + [FeatureThumb2, FeatureNEON, FeatureDB, + FeatureDSPThumb2]>; def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M", "ARM v7M", [FeatureThumb2, FeatureNoARM, FeatureDB, FeatureHWDiv]>; +def ArchV7EM : SubtargetFeature<"v7em", "ARMArchVersion", "V7EM", + "ARM v7E-M", + [FeatureThumb2, FeatureNoARM, FeatureDB, + FeatureHWDiv, FeatureDSPThumb2, + FeatureT2XtPk]>; //===----------------------------------------------------------------------===// // ARM Processors supported. @@ -192,7 +202,7 @@ def : Processor<"cortex-a9-mp", CortexA9Itineraries, // V7M Processors. def : ProcNoItin<"cortex-m3", [ArchV7M]>; -def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureVFP2, FeatureVFPOnlySP]>; +def : ProcNoItin<"cortex-m4", [ArchV7EM, FeatureVFP2, FeatureVFPOnlySP]>; //===----------------------------------------------------------------------===// // Register File Description |