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| author | Silviu Baranga <silviu.baranga@arm.com> | 2013-03-15 18:28:25 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2013-03-15 18:28:25 +0000 |
| commit | bcbf3fddef46f1f6e2f2408064c4b75e4b6c90f5 (patch) | |
| tree | 659e38348e38eed0a949be8fce08e3e9e8e9951a /lib/Target/ARM/ARMBaseInstrInfo.cpp | |
| parent | 133c0d36e1fdeda88d784017bafa8a1b22af8aca (diff) | |
| download | llvm-bcbf3fddef46f1f6e2f2408064c4b75e4b6c90f5.tar.gz llvm-bcbf3fddef46f1f6e2f2408064c4b75e4b6c90f5.tar.bz2 llvm-bcbf3fddef46f1f6e2f2408064c4b75e4b6c90f5.tar.xz | |
Adding an A15 specific optimization pass for interactions between S/D/Q registers. The pass handles all the required transformations pre-regalloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177169 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMBaseInstrInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index ed001ea24a..ed8b9cd9a1 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1125,7 +1125,7 @@ bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{ // copyPhysReg() calls. Look for VMOVS instructions that can legally be // widened to VMOVD. We prefer the VMOVD when possible because it may be // changed into a VORR that can go down the NEON pipeline. - if (!WidenVMOVS || !MI->isCopy()) + if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15()) return false; // Look for a copy between even S-registers. That is where we keep floats |