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author | Bill Wendling <isanbard@gmail.com> | 2011-10-10 07:24:23 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2011-10-10 07:24:23 +0000 |
commit | 8129d213960bac2c9d01053922866fc0f552462e (patch) | |
tree | 598a53745aa6a4daa1893e691735f96b84b86c17 /lib/Target/ARM/ARMBaseRegisterInfo.cpp | |
parent | 1f104804bf30f1457e92fa6ee958a618a958b1ad (diff) | |
download | llvm-8129d213960bac2c9d01053922866fc0f552462e.tar.gz llvm-8129d213960bac2c9d01053922866fc0f552462e.tar.bz2 llvm-8129d213960bac2c9d01053922866fc0f552462e.tar.xz |
When getting the number of bits necessary for addressing mode
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141529 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMBaseRegisterInfo.cpp')
-rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.cpp | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 7c42342229..0c8480d9ef 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -1109,11 +1109,20 @@ bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, case ARMII::AddrMode3: NumBits = 8; break; - case ARMII::AddrModeT1_s: - NumBits = 5; + case ARMII::AddrModeT1_s: { + const MachineBasicBlock &MBB = *MI->getParent(); + const MachineFunction &MF = *MBB.getParent(); + unsigned FrameReg = ARM::SP; + if (MF.getFrameInfo()->hasVarSizedObjects()) + // There are alloca()'s in this function, must reference off the frame + // pointer or base pointer instead. + FrameReg = (!hasBasePointer(MF) ?BasePtr : getFrameRegister(MF)); + + NumBits = (FrameReg == ARM::SP) ? 8 : 5; Scale = 4; isSigned = false; break; + } default: llvm_unreachable("Unsupported addressing mode!"); break; |