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author | Cameron Zwarich <zwarich@apple.com> | 2011-03-07 21:56:36 +0000 |
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committer | Cameron Zwarich <zwarich@apple.com> | 2011-03-07 21:56:36 +0000 |
commit | be2119e8e2bc7006cfd638a24367acbfda625d16 (patch) | |
tree | f6b612a7b38e222360664235d92655da3ab285d1 /lib/Target/ARM/ARMBaseRegisterInfo.cpp | |
parent | e390b3245f00627eb5c5bde5eb4ff6b6ff7c752d (diff) | |
download | llvm-be2119e8e2bc7006cfd638a24367acbfda625d16.tar.gz llvm-be2119e8e2bc7006cfd638a24367acbfda625d16.tar.bz2 llvm-be2119e8e2bc7006cfd638a24367acbfda625d16.tar.xz |
Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMBaseRegisterInfo.cpp')
-rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.cpp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index db5a31b5e6..9d7be66010 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -348,6 +348,26 @@ ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { return ARM::GPRRegisterClass; } +unsigned +ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, + MachineFunction &MF) const { + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + + switch (RC->getID()) { + default: + return 0; + case ARM::tGPRRegClassID: + return TFI->hasFP(MF) ? 4 : 5; + case ARM::GPRRegClassID: { + unsigned FP = TFI->hasFP(MF) ? 1 : 0; + return 10 - FP - (STI.isR9Reserved() ? 1 : 0); + } + case ARM::SPRRegClassID: // Currently not used as 'rep' register class. + case ARM::DPRRegClassID: + return 32 - 10; + } +} + /// getAllocationOrder - Returns the register allocation order for a specified /// register class in the form of a pair of TargetRegisterClass iterators. std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> |