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| author | Bill Wendling <isanbard@gmail.com> | 2013-06-07 05:54:19 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2013-06-07 05:54:19 +0000 |
| commit | 57148c166ab232191098492633c924fad9c44ef3 (patch) | |
| tree | 2742791240f5d1a8babb627efc05493190cadb28 /lib/Target/ARM/ARMBaseRegisterInfo.h | |
| parent | 4393f48c03300203594e22d248808f20dd59d886 (diff) | |
| download | llvm-57148c166ab232191098492633c924fad9c44ef3.tar.gz llvm-57148c166ab232191098492633c924fad9c44ef3.tar.bz2 llvm-57148c166ab232191098492633c924fad9c44ef3.tar.xz | |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183488 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMBaseRegisterInfo.h')
| -rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.h b/lib/Target/ARM/ARMBaseRegisterInfo.h index 0679919152..03b3682541 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.h +++ b/lib/Target/ARM/ARMBaseRegisterInfo.h @@ -74,7 +74,6 @@ static inline bool isARMArea3Register(unsigned Reg, bool isIOS) { class ARMBaseRegisterInfo : public ARMGenRegisterInfo { protected: - const ARMBaseInstrInfo &TII; const ARMSubtarget &STI; /// FramePtr - ARM physical register used as frame ptr. @@ -86,8 +85,7 @@ protected: unsigned BasePtr; // Can be only subclassed. - explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, - const ARMSubtarget &STI); + explicit ARMBaseRegisterInfo(const ARMSubtarget &STI); // Return the opcode that implements 'Op', or 0 if no opcode unsigned getOpcode(int Op) const; |