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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-16 23:31:16 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-16 23:31:16 +0000 |
| commit | dd5a8471526ceadf9bceb1a1221299b3db49c33a (patch) | |
| tree | 242d25989213cbe232002e2bb36bbfcbc9aaac94 /lib/Target/ARM/ARMBaseRegisterInfo.h | |
| parent | c02a6fa7d8f0ccf2e0059bc40978a466fff3fcab (diff) | |
| download | llvm-dd5a8471526ceadf9bceb1a1221299b3db49c33a.tar.gz llvm-dd5a8471526ceadf9bceb1a1221299b3db49c33a.tar.bz2 llvm-dd5a8471526ceadf9bceb1a1221299b3db49c33a.tar.xz | |
Rename TRI::getAllocationOrder() to getRawAllocationOrder().
Also switch the return type to ArrayRef<unsigned> which works out nicely
for ARM's implementation of this function because of the clever ArrayRef
constructors.
The name change indicates that the returned allocation order may contain
reserved registers as has been the case for a while.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133216 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMBaseRegisterInfo.h')
| -rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.h | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.h b/lib/Target/ARM/ARMBaseRegisterInfo.h index c60d75a689..70b6f01d6c 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.h +++ b/lib/Target/ARM/ARMBaseRegisterInfo.h @@ -134,10 +134,9 @@ public: unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const; - std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> - getAllocationOrder(const TargetRegisterClass *RC, - unsigned HintType, unsigned HintReg, - const MachineFunction &MF) const; + ArrayRef<unsigned> getRawAllocationOrder(const TargetRegisterClass *RC, + unsigned HintType, unsigned HintReg, + const MachineFunction &MF) const; unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, const MachineFunction &MF) const; |