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authorPatrik Hagglund <patrik.h.hagglund@ericsson.com>2012-12-19 11:30:36 +0000
committerPatrik Hagglund <patrik.h.hagglund@ericsson.com>2012-12-19 11:30:36 +0000
commit0340557fb830e3669c4c48a2cd99d7703bdda452 (patch)
treef371ba8556ca9b57dd63714331e48046375815be /lib/Target/ARM/ARMISelLowering.cpp
parentb8837ab8fc22bc9c1d23577e4cdfb732f710478f (diff)
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Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170532 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMISelLowering.cpp')
-rw-r--r--lib/Target/ARM/ARMISelLowering.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index c493981a31..371656417b 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -863,10 +863,10 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
// due to the common occurrence of cross class copies and subregister insertions
// and extractions.
std::pair<const TargetRegisterClass*, uint8_t>
-ARMTargetLowering::findRepresentativeClass(EVT VT) const{
+ARMTargetLowering::findRepresentativeClass(MVT VT) const{
const TargetRegisterClass *RRC = 0;
uint8_t Cost = 1;
- switch (VT.getSimpleVT().SimpleTy) {
+ switch (VT.SimpleTy) {
default:
return TargetLowering::findRepresentativeClass(VT);
// Use DPR as representative register class for all floating point