summaryrefslogtreecommitdiff
path: root/lib/Target/ARM/ARMISelLowering.cpp
diff options
context:
space:
mode:
authorPatrik Hagglund <patrik.h.hagglund@ericsson.com>2012-12-11 09:57:18 +0000
committerPatrik Hagglund <patrik.h.hagglund@ericsson.com>2012-12-11 09:57:18 +0000
commitbade0345d190427a08b2b947bc94f4d8ca5d7717 (patch)
tree978829ccb08f3461c1ede97c7490b22c4bdd9c22 /lib/Target/ARM/ARMISelLowering.cpp
parentbb2543bb0e38495cd655be3eadcb9dd008ac56d2 (diff)
downloadllvm-bade0345d190427a08b2b947bc94f4d8ca5d7717.tar.gz
llvm-bade0345d190427a08b2b947bc94f4d8ca5d7717.tar.bz2
llvm-bade0345d190427a08b2b947bc94f4d8ca5d7717.tar.xz
Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169845 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMISelLowering.cpp')
-rw-r--r--lib/Target/ARM/ARMISelLowering.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 159d4df00b..095032f46c 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -863,10 +863,10 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
// due to the common occurrence of cross class copies and subregister insertions
// and extractions.
std::pair<const TargetRegisterClass*, uint8_t>
-ARMTargetLowering::findRepresentativeClass(EVT VT) const{
+ARMTargetLowering::findRepresentativeClass(MVT VT) const{
const TargetRegisterClass *RRC = 0;
uint8_t Cost = 1;
- switch (VT.getSimpleVT().SimpleTy) {
+ switch (VT.SimpleTy) {
default:
return TargetLowering::findRepresentativeClass(VT);
// Use DPR as representative register class for all floating point