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| author | Quentin Colombet <qcolombet@apple.com> | 2013-07-23 22:34:47 +0000 |
|---|---|---|
| committer | Quentin Colombet <qcolombet@apple.com> | 2013-07-23 22:34:47 +0000 |
| commit | 17f99a991f2e270a34c53854ce80acc30754537b (patch) | |
| tree | 5c2d54fa2e1e32fe01a1a8b85db83711b2799243 /lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 00d92eee327b7ac9d91bc804843f70dea5dfc068 (diff) | |
| download | llvm-17f99a991f2e270a34c53854ce80acc30754537b.tar.gz llvm-17f99a991f2e270a34c53854ce80acc30754537b.tar.bz2 llvm-17f99a991f2e270a34c53854ce80acc30754537b.tar.xz | |
[ARM][ISel] Improve the lowering of vector loads.
When vectors are built from a single value, the ARM lowering issues a
scalar_to_vector node.
This node is then always morphed into a move from the general purpose unit to
the vector unit.
When the value comes from a load, this can be simplified into a vector load to
the right lane.
This patch changes the lowering of insert_vector_elt to expose a vector
friendly pattern in this situation.
This is a step toward fixing <rdar://problem/14170854>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186999 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 569beadc60..ea13c88be8 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -4674,7 +4674,9 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, if (ValueCounts.size() == 0) return DAG.getUNDEF(VT); - if (isOnlyLowElement) + // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR. + // Keep going if we are hitting this case. + if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode())) return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); unsigned EltSize = VT.getVectorElementType().getSizeInBits(); |