diff options
| author | Tim Northover <tnorthover@apple.com> | 2013-07-01 18:37:33 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-07-01 18:37:33 +0000 |
| commit | 40d0492cdea1023463a9902ee81b3c5251204039 (patch) | |
| tree | 16297038bae5eebd4c79285bc717e2e9c2ac376d /lib/Target/ARM/ARMISelLowering.cpp | |
| parent | c7b61c638b912eaa7f85c7794589a253a3669162 (diff) | |
| download | llvm-40d0492cdea1023463a9902ee81b3c5251204039.tar.gz llvm-40d0492cdea1023463a9902ee81b3c5251204039.tar.bz2 llvm-40d0492cdea1023463a9902ee81b3c5251204039.tar.xz | |
Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst")
Turns out I'd misread the architecture reference manual and thought
that was a load/store-store barrier, when it's not.
Thanks for pointing it out Eli!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185356 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 370962dfa5..ff8571ba03 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -2557,12 +2557,8 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, DAG.getConstant(0, MVT::i32)); } - ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1)); - AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue()); - unsigned Domain = Ord == Release ? ARM_MB::ISHST : ARM_MB::ISH; - return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), - DAG.getConstant(Domain, MVT::i32)); + DAG.getConstant(ARM_MB::ISH, MVT::i32)); } static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, |