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| author | Joey Gouly <joey.gouly@arm.com> | 2013-08-23 12:01:13 +0000 |
|---|---|---|
| committer | Joey Gouly <joey.gouly@arm.com> | 2013-08-23 12:01:13 +0000 |
| commit | a0b2d332c114571716746ba90c815cfb6f68d4ab (patch) | |
| tree | 6dabdf8d992ffc29c1936659bee46519a55f89d8 /lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 5768bb8d77892926dff0d078b1fb08c14ea791f3 (diff) | |
| download | llvm-a0b2d332c114571716746ba90c815cfb6f68d4ab.tar.gz llvm-a0b2d332c114571716746ba90c815cfb6f68d4ab.tar.bz2 llvm-a0b2d332c114571716746ba90c815cfb6f68d4ab.tar.xz | |
[ARMv8] Add CodeGen for VMAXNM/VMINNM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189103 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 7021941076..74353c1788 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -1069,6 +1069,8 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; case ARMISD::FMAX: return "ARMISD::FMAX"; case ARMISD::FMIN: return "ARMISD::FMIN"; + case ARMISD::VMAXNM: return "ARMISD::VMAX"; + case ARMISD::VMINNM: return "ARMISD::VMIN"; case ARMISD::BFI: return "ARMISD::BFI"; case ARMISD::VORRIMM: return "ARMISD::VORRIMM"; case ARMISD::VBICIMM: return "ARMISD::VBICIMM"; @@ -3276,6 +3278,20 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { // Try to generate VSEL on ARMv8. if (getSubtarget()->hasV8FP() && (TrueVal.getValueType() == MVT::f32 || TrueVal.getValueType() == MVT::f64)) { + // We can select VMAXNM/VMINNM from a compare followed by a select with the + // same operands, as follows: + // c = fcmp [ogt, olt, ugt, ult] a, b + // select c, a, b + // We only do this in unsafe-fp-math, because signed zeros and NaNs are + // handled differently than the original code sequence. + if (getTargetMachine().Options.UnsafeFPMath && LHS == TrueVal && + RHS == FalseVal) { + if (CC == ISD::SETOGT || CC == ISD::SETUGT) + return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal); + if (CC == ISD::SETOLT || CC == ISD::SETULT) + return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal); + } + bool swpCmpOps = false; bool swpVselOps = false; checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps); |