diff options
| author | Joey Gouly <joey.gouly@arm.com> | 2013-08-22 12:19:24 +0000 |
|---|---|---|
| committer | Joey Gouly <joey.gouly@arm.com> | 2013-08-22 12:19:24 +0000 |
| commit | bad8d4ca599024de8fdc6255a4b73bb294f49239 (patch) | |
| tree | 249060454db381d93d68c60b105c04f41ca56f0c /lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 1765e74c15c83db437018a3c9efabbeb4ce9cbde (diff) | |
| download | llvm-bad8d4ca599024de8fdc6255a4b73bb294f49239.tar.gz llvm-bad8d4ca599024de8fdc6255a4b73bb294f49239.tar.bz2 llvm-bad8d4ca599024de8fdc6255a4b73bb294f49239.tar.xz | |
[ARM] Constrain some register classes in EmitAtomicBinary64 so that
we pass these tests with -verify-machineinstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189006 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index f22c5b9ca4..ebfa1b118e 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -6360,6 +6360,8 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB, MRI.constrainRegClass(destlo, &ARM::rGPRRegClass); MRI.constrainRegClass(desthi, &ARM::rGPRRegClass); MRI.constrainRegClass(ptr, &ARM::rGPRRegClass); + MRI.constrainRegClass(vallo, &ARM::rGPRRegClass); + MRI.constrainRegClass(valhi, &ARM::rGPRRegClass); } MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); @@ -6467,6 +6469,8 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB, // Store if (isThumb2) { + MRI.constrainRegClass(StoreLo, &ARM::rGPRRegClass); + MRI.constrainRegClass(StoreHi, &ARM::rGPRRegClass); AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2STREXD), storesuccess) .addReg(StoreLo).addReg(StoreHi).addReg(ptr)); } else { |