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authorBenjamin Kramer <benny.kra@googlemail.com>2012-11-28 20:55:10 +0000
committerBenjamin Kramer <benny.kra@googlemail.com>2012-11-28 20:55:10 +0000
commit350c00843bad22c5391e33e9e39a78d5d0983c8c (patch)
tree1b85e673c4414ebeaed6c45c820483fb3ecf4e78 /lib/Target/ARM/ARMISelLowering.h
parent1ead68d769f27f6d68d4aaeffe4199fa2cacbc95 (diff)
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ARM: Implement CanLowerReturn so large vectors get expanded into sret.
Fixes 14337. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168809 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMISelLowering.h')
-rw-r--r--lib/Target/ARM/ARMISelLowering.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h
index 8bf803edee..9cbf866f9b 100644
--- a/lib/Target/ARM/ARMISelLowering.h
+++ b/lib/Target/ARM/ARMISelLowering.h
@@ -495,6 +495,12 @@ namespace llvm {
const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const;
+
+ virtual bool CanLowerReturn(CallingConv::ID CallConv,
+ MachineFunction &MF, bool isVarArg,
+ const SmallVectorImpl<ISD::OutputArg> &Outs,
+ LLVMContext &Context) const;
+
virtual SDValue
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,