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authorJim Grosbach <grosbach@apple.com>2011-07-25 20:38:18 +0000
committerJim Grosbach <grosbach@apple.com>2011-07-25 20:38:18 +0000
commit5f6c133d7d4451a78ffc39248fc69a8870b57c6a (patch)
treebe8dde08f5faec0473a4565f6e2ec03b1a52abdd /lib/Target/ARM/ARMInstrFormats.td
parent3ef750d4b63bce1f13f9f8381fc6523f4a388b3f (diff)
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More simple cleanup of ARM asm operand definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135958 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrFormats.td')
-rw-r--r--lib/Target/ARM/ARMInstrFormats.td36
1 files changed, 9 insertions, 27 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 37e363e74d..f79ce22f3a 100644
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -131,39 +131,15 @@ def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
// ARM special operands.
//
-def CondCodeOperand : AsmOperandClass {
- let Name = "CondCode";
- let SuperClasses = [];
-}
-
-def CCOutOperand : AsmOperandClass {
- let Name = "CCOut";
- let SuperClasses = [];
-}
-
-def MemBarrierOptOperand : AsmOperandClass {
- let Name = "MemBarrierOpt";
- let SuperClasses = [];
- let ParserMethod = "parseMemBarrierOptOperand";
+// ARM imod and iflag operands, used only by the CPS instruction.
+def imod_op : Operand<i32> {
+ let PrintMethod = "printCPSIMod";
}
def ProcIFlagsOperand : AsmOperandClass {
let Name = "ProcIFlags";
- let SuperClasses = [];
let ParserMethod = "parseProcIFlagsOperand";
}
-
-def MSRMaskOperand : AsmOperandClass {
- let Name = "MSRMask";
- let SuperClasses = [];
- let ParserMethod = "parseMSRMaskOperand";
-}
-
-// ARM imod and iflag operands, used only by the CPS instruction.
-def imod_op : Operand<i32> {
- let PrintMethod = "printCPSIMod";
-}
-
def iflags_op : Operand<i32> {
let PrintMethod = "printCPSIFlag";
let ParserMatchClass = ProcIFlagsOperand;
@@ -171,6 +147,7 @@ def iflags_op : Operand<i32> {
// ARM Predicate operand. Default to 14 = always (AL). Second part is CC
// register whose default is 0 (no register).
+def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
(ops (i32 14), (i32 zero_reg))> {
let PrintMethod = "printPredicateOperand";
@@ -178,6 +155,7 @@ def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
}
// Conditional code result for instructions whose 's' bit is set, e.g. subs.
+def CCOutOperand : AsmOperandClass { let Name = "CCOut"; }
def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
let EncoderMethod = "getCCOutOpValue";
let PrintMethod = "printSBitModifierOperand";
@@ -202,6 +180,10 @@ def setend_op : Operand<i32> {
let ParserMatchClass = SetEndAsmOperand;
}
+def MSRMaskOperand : AsmOperandClass {
+ let Name = "MSRMask";
+ let ParserMethod = "parseMSRMaskOperand";
+}
def msr_mask : Operand<i32> {
let PrintMethod = "printMSRMaskOperand";
let ParserMatchClass = MSRMaskOperand;