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| author | Owen Anderson <resistor@mac.com> | 2011-07-26 20:54:26 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-07-26 20:54:26 +0000 |
| commit | 793e79601f0fd68ba082fa2016018f80b2379460 (patch) | |
| tree | 632621c84490cf3e536448d8f7921834521848a2 /lib/Target/ARM/ARMInstrInfo.cpp | |
| parent | 45c8d2bc9cf3d0a4da10deab45e3d0d45513e19f (diff) | |
| download | llvm-793e79601f0fd68ba082fa2016018f80b2379460.tar.gz llvm-793e79601f0fd68ba082fa2016018f80b2379460.tar.bz2 llvm-793e79601f0fd68ba082fa2016018f80b2379460.tar.xz | |
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136141 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.cpp | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 4f469bb5b3..f8880ea4e0 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -31,13 +31,15 @@ unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const { switch (Opc) { default: break; case ARM::LDR_PRE: - case ARM::LDR_POST: + case ARM::LDR_POST_IMM: + case ARM::LDR_POST_REG: return ARM::LDRi12; case ARM::LDRH_PRE: case ARM::LDRH_POST: return ARM::LDRH; case ARM::LDRB_PRE: - case ARM::LDRB_POST: + case ARM::LDRB_POST_IMM: + case ARM::LDRB_POST_REG: return ARM::LDRBi12; case ARM::LDRSH_PRE: case ARM::LDRSH_POST: @@ -45,14 +47,18 @@ unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const { case ARM::LDRSB_PRE: case ARM::LDRSB_POST: return ARM::LDRSB; - case ARM::STR_PRE: - case ARM::STR_POST: + case ARM::STR_PRE_IMM: + case ARM::STR_PRE_REG: + case ARM::STR_POST_IMM: + case ARM::STR_POST_REG: return ARM::STRi12; case ARM::STRH_PRE: case ARM::STRH_POST: return ARM::STRH; - case ARM::STRB_PRE: - case ARM::STRB_POST: + case ARM::STRB_PRE_IMM: + case ARM::STRB_PRE_REG: + case ARM::STRB_POST_IMM: + case ARM::STRB_POST_REG: return ARM::STRBi12; } |