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| author | Jim Grosbach <grosbach@apple.com> | 2010-10-27 23:12:14 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-10-27 23:12:14 +0000 |
| commit | 7e3383c007f53b3a00675af225e428cb66ddf404 (patch) | |
| tree | a506d6a7aa8416c28debbaa7905253d71d2dd4d5 /lib/Target/ARM/ARMInstrInfo.cpp | |
| parent | 0bccec368a55e80a2911dcb448cdffabf6bcea98 (diff) | |
| download | llvm-7e3383c007f53b3a00675af225e428cb66ddf404.tar.gz llvm-7e3383c007f53b3a00675af225e428cb66ddf404.tar.bz2 llvm-7e3383c007f53b3a00675af225e428cb66ddf404.tar.xz | |
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index d62b93e1b1..7b40fad0e3 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -48,13 +48,13 @@ unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const { return ARM::LDRSB; case ARM::STR_PRE: case ARM::STR_POST: - return ARM::STR; + return ARM::STRi12; case ARM::STRH_PRE: case ARM::STRH_POST: return ARM::STRH; case ARM::STRB_PRE: case ARM::STRB_POST: - return ARM::STRB; + return ARM::STRBi12; } return 0; |