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| author | Mihai Popa <mihail.popa@gmail.com> | 2013-06-05 13:23:51 +0000 |
|---|---|---|
| committer | Mihai Popa <mihail.popa@gmail.com> | 2013-06-05 13:23:51 +0000 |
| commit | 2248cf590617cbe91eeb6a845ad06d675d9f2e91 (patch) | |
| tree | 2032b4f5e9451f3d7b2e511c0d61e2f69c4008b4 /lib/Target/ARM/ARMInstrInfo.td | |
| parent | 7e129466d8bf25d7e0a65a4087a30a4c07746018 (diff) | |
| download | llvm-2248cf590617cbe91eeb6a845ad06d675d9f2e91.tar.gz llvm-2248cf590617cbe91eeb6a845ad06d675d9f2e91.tar.bz2 llvm-2248cf590617cbe91eeb6a845ad06d675d9f2e91.tar.xz | |
This is a simple patch that changes RRX and RRXS to accept all registers as operands.
According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183307 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrInfo.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 89f92a589d..eb3542c5d7 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -5233,7 +5233,7 @@ def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", cc_out:$s)>; } def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", - (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>; + (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; let TwoOperandAliasConstraint = "$Rn = $Rd" in { def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, |