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| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-04 22:15:52 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-04 22:15:52 +0000 |
| commit | d3b8445d14593b76b10dc8aee4bebdcbf11443ad (patch) | |
| tree | 5b35a6ab02d14bb64df0770afa456eb37936bc8b /lib/Target/ARM/ARMInstrInfo.td | |
| parent | 23cb39a3d915d6eaa2e053cae1c3158a2fdbe5c2 (diff) | |
| download | llvm-d3b8445d14593b76b10dc8aee4bebdcbf11443ad.tar.gz llvm-d3b8445d14593b76b10dc8aee4bebdcbf11443ad.tar.bz2 llvm-d3b8445d14593b76b10dc8aee4bebdcbf11443ad.tar.xz | |
ARM sched model: Add preload instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183261 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrInfo.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index e50d1d019d..0b950695cc 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1780,7 +1780,8 @@ multiclass APreLoad<bits<1> read, bits<1> data, string opc> { def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload, !strconcat(opc, "\t$addr"), - [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> { + [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, + Sched<[WritePreLd]> { bits<4> Rt; bits<17> addr; let Inst{31-26} = 0b111101; @@ -1796,7 +1797,8 @@ multiclass APreLoad<bits<1> read, bits<1> data, string opc> { def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, !strconcat(opc, "\t$shift"), - [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> { + [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, + Sched<[WritePreLd]> { bits<17> shift; let Inst{31-26} = 0b111101; let Inst{25} = 1; // 1 for register form |