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| author | Jim Grosbach <grosbach@apple.com> | 2011-09-20 00:00:06 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-09-20 00:00:06 +0000 |
| commit | 26215425da200a7b4695b78521a7677397849ad1 (patch) | |
| tree | af6fbd55274b648957788016b1600eb885504ddd /lib/Target/ARM/ARMInstrThumb.td | |
| parent | 0efe213ed5a2c1d2647dc1306e684da6147a611e (diff) | |
| download | llvm-26215425da200a7b4695b78521a7677397849ad1.tar.gz llvm-26215425da200a7b4695b78521a7677397849ad1.tar.bz2 llvm-26215425da200a7b4695b78521a7677397849ad1.tar.xz | |
Thumb CPS definition is not disassembler only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140106 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrThumb.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index a49f988079..0748cbf0a9 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -286,8 +286,7 @@ def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", // Change Processor State is a system instruction -- for disassembly only. def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), - NoItinerary, "cps$imod $iflags", - [/* For disassembly only; pattern left blank */]>, + NoItinerary, "cps$imod $iflags", []>, T1Misc<0b0110011> { // A8.6.38 & B6.1.1 bit imod; |