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| author | Tim Northover <tnorthover@apple.com> | 2013-10-07 11:10:47 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-10-07 11:10:47 +0000 |
| commit | cf3e4cb29a5fd485f11354060bb7a99e8cfdaf09 (patch) | |
| tree | 9d2dde8a3a23df35f617e28ab1e8a04e099f2620 /lib/Target/ARM/ARMInstrThumb.td | |
| parent | ae06a63be5a1279739e0c8a2006e72f4bc687d57 (diff) | |
| download | llvm-cf3e4cb29a5fd485f11354060bb7a99e8cfdaf09.tar.gz llvm-cf3e4cb29a5fd485f11354060bb7a99e8cfdaf09.tar.bz2 llvm-cf3e4cb29a5fd485f11354060bb7a99e8cfdaf09.tar.xz | |
ARM: allow cortex-m0 to use hint instructions
The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have
been ported across to the v6M architecture. Fortunately, v6M seems to sit
nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it
fairly easily.
rdar://problem/15144406
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192097 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrThumb.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 458254ee62..9712ed3274 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -271,23 +271,23 @@ class T1SystemEncoding<bits<8> opc> def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>, T1SystemEncoding<0x00>, // A8.6.110 - Requires<[IsThumb2]>; + Requires<[IsThumb, HasV6M]>; def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>, T1SystemEncoding<0x10>, // A8.6.410 - Requires<[IsThumb2]>; + Requires<[IsThumb, HasV6M]>; def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>, T1SystemEncoding<0x20>, // A8.6.408 - Requires<[IsThumb2]>; + Requires<[IsThumb, HasV6M]>; def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>, T1SystemEncoding<0x30>, // A8.6.409 - Requires<[IsThumb2]>; + Requires<[IsThumb, HasV6M]>; def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>, T1SystemEncoding<0x40>, // A8.6.157 - Requires<[IsThumb2]>; + Requires<[IsThumb, HasV6M]>; def tSEVL : T1pI<(outs), (ins), NoItinerary, "sevl", "", [(int_arm_sevl)]>, T1SystemEncoding<0x50>, |