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| author | Amaury de la Vieuville <amaury.dlv@gmail.com> | 2013-06-14 11:21:35 +0000 |
|---|---|---|
| committer | Amaury de la Vieuville <amaury.dlv@gmail.com> | 2013-06-14 11:21:35 +0000 |
| commit | a768a4954818456fa6fe2077a3cbe75979025c15 (patch) | |
| tree | 49f84d287cd90d354fa218b9f0c49555ce6b0278 /lib/Target/ARM/ARMInstrThumb2.td | |
| parent | d25ec760cbf93e8c8493eaab2265c8bb8cf1d233 (diff) | |
| download | llvm-a768a4954818456fa6fe2077a3cbe75979025c15.tar.gz llvm-a768a4954818456fa6fe2077a3cbe75979025c15.tar.bz2 llvm-a768a4954818456fa6fe2077a3cbe75979025c15.tar.xz | |
ARM: fix thumb coprocessor instruction with pre-writeback disassembly
was stc2 p0, c0, [r0]!
instead of stc2 p0, c0, [r0,#0]!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183975 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrThumb2.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index ff21bf70ec..8b114a8326 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -3632,7 +3632,7 @@ multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> { let DecoderMethod = "DecodeCopMemInstruction"; } def _PRE : T2CI<op31_28, - (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), + (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), asm, "\t$cop, $CRd, $addr!"> { bits<13> addr; bits<4> cop; |