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| author | Joey Gouly <joey.gouly@arm.com> | 2013-08-22 15:29:11 +0000 |
|---|---|---|
| committer | Joey Gouly <joey.gouly@arm.com> | 2013-08-22 15:29:11 +0000 |
| commit | 35eab1db2f21aee9678fe946a5d983a67285e7e4 (patch) | |
| tree | 6d6c05c460860ecd13f344a8422c89a3ca05b9c7 /lib/Target/ARM/ARMInstrVFP.td | |
| parent | 3f256c2e0b4417288e3191e67cb16177c8d8b2a7 (diff) | |
| download | llvm-35eab1db2f21aee9678fe946a5d983a67285e7e4.tar.gz llvm-35eab1db2f21aee9678fe946a5d983a67285e7e4.tar.bz2 llvm-35eab1db2f21aee9678fe946a5d983a67285e7e4.tar.xz | |
[ARMv8] Add CodeGen support for VSEL.
This uses the ARMcmov pattern that Tim cleaned up in r188995.
Thanks to Simon Tatham for his floating point help!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189024 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrVFP.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrVFP.td | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index c6b8bc3f92..b4df4d787e 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -333,24 +333,28 @@ def VNMULS : ASbI<0b11100, 0b10, 1, 0, let D = VFPNeonA8Domain; } -multiclass vsel_inst<string op, bits<2> opc> { - let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in { +multiclass vsel_inst<string op, bits<2> opc, int CC> { + let DecoderNamespace = "VFPV8", PostEncoderMethod = "", + Uses = [CPSR], AddedComplexity = 4 in { def S : ASbInp<0b11100, opc, 0, (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"), - []>, Requires<[HasV8FP]>; + [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>, + Requires<[HasV8FP]>; def D : ADbInp<0b11100, opc, 0, (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"), - []>, Requires<[HasV8FP]>; + [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>, + Requires<[HasV8FP]>; } } -defm VSELGT : vsel_inst<"gt", 0b11>; -defm VSELGE : vsel_inst<"ge", 0b10>; -defm VSELEQ : vsel_inst<"eq", 0b00>; -defm VSELVS : vsel_inst<"vs", 0b01>; +// The CC constants here match ARMCC::CondCodes. +defm VSELGT : vsel_inst<"gt", 0b11, 12>; +defm VSELGE : vsel_inst<"ge", 0b10, 10>; +defm VSELEQ : vsel_inst<"eq", 0b00, 0>; +defm VSELVS : vsel_inst<"vs", 0b01, 6>; multiclass vmaxmin_inst<string op, bit opc> { let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in { |