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| author | Jim Grosbach <grosbach@apple.com> | 2012-04-10 00:13:07 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2012-04-10 00:13:07 +0000 |
| commit | 2d620c571cb53993b788893b6ef73a6e2805411f (patch) | |
| tree | acec26762b55fc3339c0cc66c188042b11cf4871 /lib/Target/ARM/ARMLoadStoreOptimizer.cpp | |
| parent | 23f369d1fe56aa9558f141acec24fc1485019227 (diff) | |
| download | llvm-2d620c571cb53993b788893b6ef73a6e2805411f.tar.gz llvm-2d620c571cb53993b788893b6ef73a6e2805411f.tar.bz2 llvm-2d620c571cb53993b788893b6ef73a6e2805411f.tar.xz | |
ARM LDR/LDRT has the same encoding collision as STR/STRT.
Generalized logic of r154141.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154362 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index b632c78700..9ef2ace29c 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -1160,6 +1160,11 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB, unsigned NewOpc = (isLd) ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); + // Be extra careful for thumb2. t2LDRi8 can't reference a zero offset, + // so adjust and use t2LDRi12 here for that. + unsigned NewOpc2 = (isLd) + ? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) + : (isT2 ? (OffImm+4 < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); DebugLoc dl = MBBI->getDebugLoc(); // If this is a load and base register is killed, it may have been // re-defed by the load, make sure the first load does not clobber it. @@ -1167,13 +1172,11 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB, (BaseKill || OffKill) && (TRI->regsOverlap(EvenReg, BaseReg))) { assert(!TRI->regsOverlap(OddReg, BaseReg)); - InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc, + InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc2, OddReg, OddDeadKill, false, BaseReg, false, BaseUndef, false, OffUndef, Pred, PredReg, TII, isT2); NewBBI = llvm::prior(MBBI); - // Be extra careful for thumb2. t2LDRi8 can't reference a zero offset, - // so adjust and use t2LDRi12 here for that. if (isT2 && NewOpc == ARM::t2LDRi8 && OffImm+4 >= 0) NewOpc = ARM::t2LDRi12; InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc, @@ -1197,11 +1200,7 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB, BaseReg, false, BaseUndef, false, OffUndef, Pred, PredReg, TII, isT2); NewBBI = llvm::prior(MBBI); - // Be extra careful for thumb2. t2STRi8 can't reference a zero offset, - // so adjust and use t2STRi12 here for that. - if (isT2 && NewOpc == ARM::t2STRi8 && OffImm+4 >= 0) - NewOpc = ARM::t2STRi12; - InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc, + InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc2, OddReg, OddDeadKill, OddUndef, BaseReg, BaseKill, BaseUndef, OffKill, OffUndef, Pred, PredReg, TII, isT2); |