diff options
| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-04-05 05:01:06 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-04-05 05:01:06 +0000 |
| commit | fc61e635fd09e0cb852313f5533fb7fe694158fb (patch) | |
| tree | 370f3671b3841ad3d48faa64a49253629cf4eef7 /lib/Target/ARM/ARMSchedule.td | |
| parent | 3341538be65694176c91c3d31a70e1154c998cbd (diff) | |
| download | llvm-fc61e635fd09e0cb852313f5533fb7fe694158fb.tar.gz llvm-fc61e635fd09e0cb852313f5533fb7fe694158fb.tar.bz2 llvm-fc61e635fd09e0cb852313f5533fb7fe694158fb.tar.xz | |
ARM scheduler model: Add scheduler info to more instructions and resource
descriptions for compares
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178844 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMSchedule.td')
| -rw-r--r-- | lib/Target/ARM/ARMSchedule.td | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td index 136a90aa95..2d088de96e 100644 --- a/lib/Target/ARM/ARMSchedule.td +++ b/lib/Target/ARM/ARMSchedule.td @@ -64,6 +64,11 @@ def WriteALUsr : SchedWrite; // Shift by register. def WriteALUSsr : SchedWrite; // Shift by register (flag setting). def ReadALUsr : SchedRead; // Some operands are read later. +// Compares. +def WriteCMP : SchedWrite; +def WriteCMPsi : SchedWrite; +def WriteCMPsr : SchedWrite; + // Define TII for use in SchedVariant Predicates. def : PredicateProlog<[{ const ARMBaseInstrInfo *TII = |