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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-11 23:41:41 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-11 23:41:41 +0000 |
| commit | 08cec1ef27d4f27320f871cf17fd742196465232 (patch) | |
| tree | 206e9ecc6b1ea55efdbf1ce5b357e464923f4af4 /lib/Target/ARM/ARMScheduleA8.td | |
| parent | 633e7023177837537adabf775395ebe7ab51b38f (diff) | |
| download | llvm-08cec1ef27d4f27320f871cf17fd742196465232.tar.gz llvm-08cec1ef27d4f27320f871cf17fd742196465232.tar.bz2 llvm-08cec1ef27d4f27320f871cf17fd742196465232.tar.xz | |
More ARM scheduling itinerary fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116266 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA8.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA8.td | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td index e318950b0f..7573182434 100644 --- a/lib/Target/ARM/ARMScheduleA8.td +++ b/lib/Target/ARM/ARMScheduleA8.td @@ -665,12 +665,25 @@ def CortexA8Itineraries : ProcessorItineraries< InstrItinData<IIC_VBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_NPipe]>], [5, 2, 2]>, // + // VPADD, etc. + InstrItinData<IIC_VPBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<1, [A8_NPipe]>], [5, 2, 2]>, + // + // Double-register FP VMUL + InstrItinData<IIC_VFMULD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<1, [A8_NPipe]>], [5, 2, 1]>, + + // // Quad-register FP Binary // Result written in N5, but that is relative to the last cycle of multicycle, // so we use 6 for those cases InstrItinData<IIC_VBINQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<2, [A8_NPipe]>], [6, 2, 2]>, // + // Quad-register FP VMUL + InstrItinData<IIC_VFMULQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<1, [A8_NPipe]>], [6, 2, 1]>, + // // Move InstrItinData<IIC_VMOV, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_NPipe]>], [1, 1]>, |