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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-09 04:07:58 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-09 04:07:58 +0000 |
| commit | 10dc63feeb7847f867a6f35179312f4079981ad3 (patch) | |
| tree | 7bf5a8373e146f6df2f5ab014ef6d3f87732b727 /lib/Target/ARM/ARMScheduleA8.td | |
| parent | e90ea139f47752eb122af756a5714ef0b3756298 (diff) | |
| download | llvm-10dc63feeb7847f867a6f35179312f4079981ad3.tar.gz llvm-10dc63feeb7847f867a6f35179312f4079981ad3.tar.bz2 llvm-10dc63feeb7847f867a6f35179312f4079981ad3.tar.xz | |
Add VLD4 scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116143 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA8.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA8.td | 25 |
1 files changed, 22 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td index 6c4cf8f122..fc6ad34005 100644 --- a/lib/Target/ARM/ARMScheduleA8.td +++ b/lib/Target/ARM/ARMScheduleA8.td @@ -390,7 +390,7 @@ def CortexA8Itineraries : ProcessorItineraries< // // VLD1 InstrItinData<IIC_VLD1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NLSPipe]>, + InstrStage<1, [A8_NLSPipe], 1>, InstrStage<1, [A8_LSPipe]>]>, // VLD1x2 InstrItinData<IIC_VLD1x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, @@ -496,8 +496,27 @@ def CortexA8Itineraries : ProcessorItineraries< // // VLD4 InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NLSPipe]>, - InstrStage<1, [A8_LSPipe]>], [2, 2, 2, 2, 1]>, + InstrStage<4, [A8_NLSPipe], 1>, + InstrStage<4, [A8_LSPipe]>], + [3, 3, 4, 4, 1]>, + // + // VLD4ln + InstrItinData<IIC_VLD4ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<5, [A8_NLSPipe], 1>, + InstrStage<5, [A8_LSPipe]>], + [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>, + // + // VLD4u + InstrItinData<IIC_VLD4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<4, [A8_NLSPipe], 1>, + InstrStage<4, [A8_LSPipe]>], + [3, 3, 4, 4, 2, 1]>, + // + // VLD4lnu + InstrItinData<IIC_VLD4lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<5, [A8_NLSPipe], 1>, + InstrStage<5, [A8_LSPipe]>], + [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>, // // VST // FIXME: We don't model this instruction properly |