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authorEvan Cheng <evan.cheng@apple.com>2010-09-29 22:42:35 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-09-29 22:42:35 +0000
commit3881cb7a5d54c0011b40997adcd742e1c7b91abd (patch)
treeaeeed4ca9a75fe9bb1619a0595be07a06bb3edc2 /lib/Target/ARM/ARMScheduleA8.td
parent6406d004c98af569632ecc1db5d852ac7da9b7c8 (diff)
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Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
pipeline forwarding path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115098 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA8.td')
-rw-r--r--lib/Target/ARM/ARMScheduleA8.td1
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td
index e6b2beae03..8962ec93ef 100644
--- a/lib/Target/ARM/ARMScheduleA8.td
+++ b/lib/Target/ARM/ARMScheduleA8.td
@@ -36,6 +36,7 @@ def CortexA8Itineraries : ProcessorItineraries<
InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>,
InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
+ InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>,
InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>,
//
// Bitwise Instructions that produce a result