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| author | Evan Cheng <evan.cheng@apple.com> | 2010-09-29 00:27:46 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-09-29 00:27:46 +0000 |
| commit | 7e1bf305cfecbaee859405468b769650efe68f1a (patch) | |
| tree | f64a36c7a397ececbfa69ef7a0c237e0f019a5f3 /lib/Target/ARM/ARMScheduleA8.td | |
| parent | 63d66eed16a6ee4e838f2f7a4c8299def0722c20 (diff) | |
| download | llvm-7e1bf305cfecbaee859405468b769650efe68f1a.tar.gz llvm-7e1bf305cfecbaee859405468b769650efe68f1a.tar.bz2 llvm-7e1bf305cfecbaee859405468b769650efe68f1a.tar.xz | |
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115008 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA8.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA8.td | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td index 6bec63734d..6b9b964e42 100644 --- a/lib/Target/ARM/ARMScheduleA8.td +++ b/lib/Target/ARM/ARMScheduleA8.td @@ -38,6 +38,12 @@ def CortexA8Itineraries : ProcessorItineraries< InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>, // + // Bitwise Instructions that produce a result + InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, + InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>, + InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, + InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>, + // // Unary Instructions that produce a result InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, @@ -45,6 +51,7 @@ def CortexA8Itineraries : ProcessorItineraries< // Zero and sign extension instructions InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>, InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, + InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>, // // Compare instructions InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>, |