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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-09 01:45:34 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-09 01:45:34 +0000 |
| commit | 84f69e8436d522cb3a772766ba67a1d7658dfdf5 (patch) | |
| tree | f023e217529142fa674132669261d86fdd90502f /lib/Target/ARM/ARMScheduleA8.td | |
| parent | 40bb6836f64ca5c60f759896805fcc163e305a4d (diff) | |
| download | llvm-84f69e8436d522cb3a772766ba67a1d7658dfdf5.tar.gz llvm-84f69e8436d522cb3a772766ba67a1d7658dfdf5.tar.bz2 llvm-84f69e8436d522cb3a772766ba67a1d7658dfdf5.tar.xz | |
Finish vld3 and vld4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116140 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA8.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA8.td | 33 |
1 files changed, 26 insertions, 7 deletions
diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td index e711839845..6c4cf8f122 100644 --- a/lib/Target/ARM/ARMScheduleA8.td +++ b/lib/Target/ARM/ARMScheduleA8.td @@ -441,39 +441,58 @@ def CortexA8Itineraries : ProcessorItineraries< [2, 2, 1]>, // // VLD2x2 - InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VLD2x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<3, [A8_NLSPipe], 1>, InstrStage<3, [A8_LSPipe]>], [2, 2, 3, 3, 1]>, // // VLD2ln - InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VLD2ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<3, [A8_NLSPipe], 1>, InstrStage<3, [A8_LSPipe]>], [3, 3, 1, 1, 1, 1]>, // // VLD2u - InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VLD2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_NLSPipe], 1>, InstrStage<1, [A8_LSPipe]>], [2, 2, 2, 1, 1, 1]>, // // VLD2x2u - InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VLD2x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<3, [A8_NLSPipe], 1>, InstrStage<3, [A8_LSPipe]>], [2, 2, 3, 3, 2, 1]>, // // VLD2lnu - InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrItinData<IIC_VLD2lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<3, [A8_NLSPipe], 1>, InstrStage<3, [A8_LSPipe]>], [3, 3, 2, 1, 1, 1, 1, 1]>, // // VLD3 InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NLSPipe]>, - InstrStage<1, [A8_LSPipe]>], [2, 2, 2, 1]>, + InstrStage<4, [A8_NLSPipe], 1>, + InstrStage<4, [A8_LSPipe]>], + [3, 3, 4, 1]>, + // + // VLD3ln + InstrItinData<IIC_VLD3ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<5, [A8_NLSPipe], 1>, + InstrStage<5, [A8_LSPipe]>], + [4, 4, 5, 1, 1, 1, 1, 2]>, + // + // VLD3u + InstrItinData<IIC_VLD3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<4, [A8_NLSPipe], 1>, + InstrStage<4, [A8_LSPipe]>], + [3, 3, 4, 2, 1]>, + // + // VLD3lnu + InstrItinData<IIC_VLD3lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<5, [A8_NLSPipe], 1>, + InstrStage<5, [A8_LSPipe]>], + [4, 4, 5, 2, 1, 1, 1, 1, 1, 2]>, // // VLD4 InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, |