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| author | Evan Cheng <evan.cheng@apple.com> | 2010-11-03 00:40:22 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-11-03 00:40:22 +0000 |
| commit | 41957f6eb2271e5f1981b32a873d1b58217c6411 (patch) | |
| tree | 454532643a4154de45f211dd4ea2b7512c606607 /lib/Target/ARM/ARMScheduleA9.td | |
| parent | 5005e27f9714f0eaa5b8b7a5a1f6751afa163f07 (diff) | |
| download | llvm-41957f6eb2271e5f1981b32a873d1b58217c6411.tar.gz llvm-41957f6eb2271e5f1981b32a873d1b58217c6411.tar.bz2 llvm-41957f6eb2271e5f1981b32a873d1b58217c6411.tar.xz | |
Modify scheduling itineraries to correct instruction latencies (not operand
latencies) of loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118134 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA9.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 154 |
1 files changed, 77 insertions, 77 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index fb2c24d161..d5ab5dcc87 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -173,88 +173,88 @@ def CortexA9Itineraries : ProcessorItineraries< // Immediate offset InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 1], [A9_LdBypass]>, InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [4, 1], [A9_LdBypass]>, // FIXME: If address is 64-bit aligned, AGU cycles is 1. InstrItinData<IIC_iLoad_d_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 3, 1], [A9_LdBypass]>, // // Register offset InstrItinData<IIC_iLoad_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 1, 1], [A9_LdBypass]>, InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [4, 1, 1], [A9_LdBypass]>, InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 3, 1, 1], [A9_LdBypass]>, // // Scaled register offset InstrItinData<IIC_iLoad_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, - InstrStage<1, [A9_LSUnit]>], + InstrStage<1, [A9_AGU], 0>, + InstrStage<1, [A9_LSUnit], 0>], [4, 1, 1], [A9_LdBypass]>, InstrItinData<IIC_iLoad_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [5, 1, 1], [A9_LdBypass]>, // // Immediate offset with update InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 2, 1], [A9_LdBypass]>, InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [4, 3, 1], [A9_LdBypass]>, // // Register offset with update InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 2, 1, 1], [A9_LdBypass]>, InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [4, 3, 1, 1], [A9_LdBypass]>, InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 3, 1, 1], [A9_LdBypass]>, // // Scaled register offset with update InstrItinData<IIC_iLoad_siu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [4, 3, 1, 1], [A9_LdBypass]>, InstrItinData<IIC_iLoad_bh_siu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [5, 4, 1, 1], [A9_LdBypass]>, // @@ -305,7 +305,7 @@ def CortexA9Itineraries : ProcessorItineraries< // iLoadi + iALUr for t2LDRpci_pic. InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>, InstrStage<1, [A9_ALU0, A9_ALU1]>], [2, 1]>, @@ -315,7 +315,7 @@ def CortexA9Itineraries : ProcessorItineraries< // Immediate offset InstrItinData<IIC_iStore_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1]>, InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, @@ -330,7 +330,7 @@ def CortexA9Itineraries : ProcessorItineraries< // Register offset InstrItinData<IIC_iStore_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>, InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, @@ -344,7 +344,7 @@ def CortexA9Itineraries : ProcessorItineraries< // Scaled register offset InstrItinData<IIC_iStore_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>, InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, @@ -354,7 +354,7 @@ def CortexA9Itineraries : ProcessorItineraries< // Immediate offset with update InstrItinData<IIC_iStore_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1, 1]>, InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, @@ -364,7 +364,7 @@ def CortexA9Itineraries : ProcessorItineraries< // Register offset with update InstrItinData<IIC_iStore_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>, InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, @@ -381,7 +381,7 @@ def CortexA9Itineraries : ProcessorItineraries< // Scaled register offset with update InstrItinData<IIC_iStore_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>, InstrItinData<IIC_iStore_bh_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, @@ -393,13 +393,13 @@ def CortexA9Itineraries : ProcessorItineraries< // Store multiple InstrItinData<IIC_iStore_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<2, [A9_LSUnit]>]>, // // Store multiple + update InstrItinData<IIC_iStore_mu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<2, [A9_LSUnit]>], [2]>, // Branch @@ -657,7 +657,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1]>, // @@ -667,7 +667,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1]>, // @@ -676,7 +676,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1, 1, 1]>, // // FP Load Multiple + update @@ -684,7 +684,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>, // // Single-precision FP Store @@ -692,7 +692,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1]>, // @@ -701,7 +701,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1]>, // @@ -710,7 +710,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1, 1, 1]>, // // FP Store Multiple + update @@ -718,7 +718,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>, // NEON // VLD1 @@ -727,7 +727,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 1]>, // VLD1x2 @@ -735,7 +735,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 2, 1]>, // VLD1x3 @@ -743,7 +743,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 2, 3, 1]>, // VLD1x4 @@ -751,7 +751,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 2, 3, 3, 1]>, // VLD1u @@ -759,7 +759,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 2, 1]>, // VLD1x2u @@ -767,7 +767,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 2, 2, 1]>, // VLD1x3u @@ -775,7 +775,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 2, 3, 2, 1]>, // VLD1x4u @@ -783,7 +783,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 2, 3, 3, 2, 1]>, // @@ -811,7 +811,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsN], 0, Required>, // Extra latency cycles since wbck is 7 cycles InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [3, 3, 1]>, // @@ -820,7 +820,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [3, 4, 3, 4, 1]>, // @@ -829,7 +829,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [4, 4, 1, 1, 1, 1]>, // @@ -839,7 +839,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsN], 0, Required>, // Extra latency cycles since wbck is 7 cycles InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [3, 3, 2, 1, 1, 1]>, // @@ -848,7 +848,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [3, 4, 3, 4, 2, 1]>, // @@ -857,7 +857,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [4, 4, 2, 1, 1, 1, 1, 1]>, // @@ -866,7 +866,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<10,[A9_DRegsVFP], 0, Reserved>, - InstrStage<4, [A9_NPipe], 1>, + InstrStage<4, [A9_NPipe], 0>, InstrStage<4, [A9_LSUnit]>], [4, 4, 5, 1]>, // @@ -875,7 +875,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<11,[A9_DRegsVFP], 0, Reserved>, - InstrStage<5, [A9_NPipe], 1>, + InstrStage<5, [A9_NPipe], 0>, InstrStage<5, [A9_LSUnit]>], [5, 5, 6, 1, 1, 1, 1, 2]>, // @@ -884,7 +884,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<10,[A9_DRegsVFP], 0, Reserved>, - InstrStage<4, [A9_NPipe], 1>, + InstrStage<4, [A9_NPipe], 0>, InstrStage<4, [A9_LSUnit]>], [4, 4, 5, 2, 1]>, // @@ -893,7 +893,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<11,[A9_DRegsVFP], 0, Reserved>, - InstrStage<5, [A9_NPipe], 1>, + InstrStage<5, [A9_NPipe], 0>, InstrStage<5, [A9_LSUnit]>], [5, 5, 6, 2, 1, 1, 1, 1, 1, 2]>, // @@ -902,7 +902,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<10,[A9_DRegsVFP], 0, Reserved>, - InstrStage<4, [A9_NPipe], 1>, + InstrStage<4, [A9_NPipe], 0>, InstrStage<4, [A9_LSUnit]>], [4, 4, 5, 5, 1]>, // @@ -911,7 +911,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<11,[A9_DRegsVFP], 0, Reserved>, - InstrStage<5, [A9_NPipe], 1>, + InstrStage<5, [A9_NPipe], 0>, InstrStage<5, [A9_LSUnit]>], [5, 5, 6, 6, 1, 1, 1, 1, 2, 2]>, // @@ -920,7 +920,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<10,[A9_DRegsVFP], 0, Reserved>, - InstrStage<4, [A9_NPipe], 1>, + InstrStage<4, [A9_NPipe], 0>, InstrStage<4, [A9_LSUnit]>], [4, 4, 5, 5, 2, 1]>, // @@ -929,7 +929,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<11,[A9_DRegsVFP], 0, Reserved>, - InstrStage<5, [A9_NPipe], 1>, + InstrStage<5, [A9_NPipe], 0>, InstrStage<5, [A9_LSUnit]>], [5, 5, 6, 6, 2, 1, 1, 1, 1, 1, 2, 2]>, // @@ -938,7 +938,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [1, 1, 1]>, // @@ -947,7 +947,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [1, 1, 1, 1]>, // @@ -956,7 +956,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2]>, // @@ -965,7 +965,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2, 2]>, // @@ -974,7 +974,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 1, 1, 1, 1]>, // @@ -983,7 +983,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1]>, // @@ -992,7 +992,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2]>, // @@ -1001,7 +1001,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // @@ -1028,7 +1028,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [1, 1, 1, 1]>, // @@ -1037,7 +1037,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2, 2]>, // @@ -1046,7 +1046,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1]>, // @@ -1055,7 +1055,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // @@ -1064,7 +1064,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [1, 1, 1, 1]>, // @@ -1073,7 +1073,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1]>, // @@ -1082,7 +1082,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2]>, // @@ -1091,7 +1091,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2]>, // @@ -1100,7 +1100,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2]>, // @@ -1109,7 +1109,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2]>, // @@ -1118,7 +1118,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2, 2]>, // @@ -1127,7 +1127,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // @@ -1136,7 +1136,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2, 2]>, // @@ -1145,7 +1145,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2, 2]>, |