diff options
| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-04 22:15:46 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-04 22:15:46 +0000 |
| commit | 611c6e135910779a8d1ed6db023d87f19799f6ac (patch) | |
| tree | 71d1b3212d87e93502476173767bb85cce64cc13 /lib/Target/ARM/ARMScheduleA9.td | |
| parent | ede7eeae328d455b00d600639adacda695a499b6 (diff) | |
| download | llvm-611c6e135910779a8d1ed6db023d87f19799f6ac.tar.gz llvm-611c6e135910779a8d1ed6db023d87f19799f6ac.tar.bz2 llvm-611c6e135910779a8d1ed6db023d87f19799f6ac.tar.xz | |
ARM sched model: Add divsion, loads, branches, vfp cvt
Add some generic SchedWrites and assign resources for Swift and Cortex A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183257 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA9.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 9739ed20ce..884c780399 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -2493,4 +2493,11 @@ def : SchedAlias<ReadALUsr, A9ReadALU>; def : SchedAlias<WriteCMP, A9WriteALU>; def : SchedAlias<WriteCMPsi, A9WriteALU>; def : SchedAlias<WriteCMPsr, A9WriteALU>; +def : WriteRes<WriteDiv, []> { let Latency = 0; } + +def : WriteRes<WriteBr, [A9UnitB]>; +def : WriteRes<WriteBrL, [A9UnitB]>; +def : WriteRes<WriteBrTbl, [A9UnitB]>; +def : WriteRes<WritePreLd, []>; +def : SchedAlias<WriteCvtFP, A9WriteF>; } // SchedModel = CortexA9Model |