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| author | Bob Wilson <bob.wilson@apple.com> | 2010-11-27 06:35:09 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-11-27 06:35:09 +0000 |
| commit | 8d412946643f048daa9d76b4f021a172341ea045 (patch) | |
| tree | 1b72742427d13785dcec32631af9f4187006982e /lib/Target/ARM/ARMScheduleA9.td | |
| parent | ad1252498d37fdf32c92569fe35bf09bb6e78caa (diff) | |
| download | llvm-8d412946643f048daa9d76b4f021a172341ea045.tar.gz llvm-8d412946643f048daa9d76b4f021a172341ea045.tar.bz2 llvm-8d412946643f048daa9d76b4f021a172341ea045.tar.xz | |
Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions.
I added these instructions recently but I have no idea where these "1"
values in the NextCycles field came from. As far as I can tell now,
these instruction stages are clearly intended to overlap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120193 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA9.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 4a398c4656..14bfdb7578 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -800,7 +800,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [4, 1, 1, 1]>, // @@ -809,7 +809,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [4, 2, 1, 1, 1, 1]>, // @@ -1018,7 +1018,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [1, 1, 1]>, // @@ -1027,7 +1027,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1]>, // |