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| author | Andrew Trick <atrick@apple.com> | 2012-08-08 02:44:16 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-08-08 02:44:16 +0000 |
| commit | d43b5c97cff06d7840b974ca84fa0639d2567968 (patch) | |
| tree | eb9de873f2da7cc46629dc7c007658844382a9e8 /lib/Target/ARM/ARMScheduleA9.td | |
| parent | 3c417554caedde3a333755916701c8380606342a (diff) | |
| download | llvm-d43b5c97cff06d7840b974ca84fa0639d2567968.tar.gz llvm-d43b5c97cff06d7840b974ca84fa0639d2567968.tar.bz2 llvm-d43b5c97cff06d7840b974ca84fa0639d2567968.tar.xz | |
Added MispredictPenalty to SchedMachineModel.
This replaces an existing subtarget hook on ARM and allows standard
CodeGen passes to potentially use the property.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA9.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 738974e5f3..7bc590f947 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -1886,6 +1886,7 @@ def CortexA9Model : SchedMachineModel { let LoadLatency = 2; // Optimistic load latency assuming bypass. // This is overriden by OperandCycles if the // Itineraries are queried instead. + let MispredictPenalty = 8; // Based on estimate of pipeline depth. let Itineraries = CortexA9Itineraries; } |